Improved bonding technology helped Toshiba and IBM Corp. develop a higher performance CMOS FET. CMOS has traditionally played a central role in semiconductor design, a position now under threat as scaling approaches physical limits that inhibit further advances in transistor performance and migration to finer process technology. The answer to these challenges includes adoption of new structures and new materials such as High-K and metal gates. Another way to improve performance is to increase the mobility of electrons, or holes, through device channels. Mobility may be increased by using direct silicon bonding (DSB) wafers, a bulk-CMOS-hybrid type wafer that bonds (100) and (110) substrates.
The new methodology involves obtaining standard (100) silicon wafers by rotating the plane of the (100) layer by 45° and thinning the DSB layer of the (110) substrate. The result is a 10% improvement in ring-oscillator delay compared with conventional DSB substrate 0° (100) wafers and a 30% improvement compared with the standard (100) wafers. This bonding development can be integrated with technologies to reach even higher performance levels.
CMOS makes use of two types of transistors: positively-charged field effect transistors (PFETs) and negatively charged FETs (NFETs). For PFETs, hole mobility is known to achieve higher performance on a substrate with (110) surface orientation than on a substrate with (100) surface orientation. However, for NFETs, electric charge mobility deteriorates on a substrate with (110) surface orientation compared with mobility on a substrate (100) surface orientation. Toshiba and IBM used hybrid-orientation technology fabricated on a hybrid substrate with different crystal orientations to achieve significant PFET performance improvement without any deterioration in NFET performance.