Manufacturing Basics: Component Soldering Issues

Sept. 4, 2012
Sometimes power electronics engineers get involved in manufacturing processes that they may not understand fully. One such issue is providing consistency from one solder joint to another to prevent what is known as “tombstoning,” where a component fails to be assembled properly.

Tombstoning is a defect where a two-leaded, wrap-around lead-style termination chip component fails to lay down appropriately and allow solder to simultaneously make a required electrical/mechanical connection to the target pads (Fig.1). As a result, only one side of a two-leaded chip component may be soldered to the target pad and the sister termination of the chip component may not come in contact with the target pad. In such instances, we can assume that one side of a two-leaded component may not be adequately soldered. As a result it might often appear as an additional defect—a missing part.

Clearly, circuit card assemblies (CCA) that demonstrate tombstone characteristics require special attention, due in part to the high risk of unacceptably long delivery times they can cause and the lengthy rework times associated with printed circuit board (PCB) repair and the need to replace parts. Because no direct cause of—or resolution to—any single aspect of tombstone had ever been conclusively identified, an in-depth investigation was initiated to identify the cause, or causes, and ultimately resolve tombstoning. After diligent study, both cause and resolution have now been identified.

As our effort began, several key questions were identified:

  • Are process defects the responsibility of manufacturers? If so, or if not, why?
  • Is changing a CAD library for each manufacturer always sufficient to avoid the problem of tombstoning?
  • Aren’t quality, on-time delivery and cost solely the responsibility of manufacturers?

Procedural Missteps

Unfortunately, procedural missteps can occur at any point in the manufacturing process and a defect may not be reported to the customer. To determine whether the defect is process- or design-related—is a challenging task fraught with great difficulty. Preliminary assumptions can range from poor manufacturer process controls, to failure to ensure sufficient solder volume and deposition, to target pad insufficiency, to the need to incorporate a home-plate design, to the need for CAD designers to create specialized pad geometry (known as home-plate design). Each assumption must be thoroughly evaluated if the tombstone cause is to ultimately be eliminated.

Certainly, surface-mount technology (SMT) process controls, pad geometry and stencil design may all be factors in the development of a tombstone effect in products. However, essential questions still remain: If the process controls are tuned, what causes the chip component to tombstone? And, if the stencil and pad geometry are of home-plate design, why is the tombstone effect still present? We felt these questions needed to be answered.

In hopes of eliminating the tombstone problem altogether, studies have been initiated that looked at many potential factors, including solder composition—specifically, varying grain sizes; tin/lead (SnPb) vs. lead-free; and dual reflow solderpaste, where one alloy would reflow and secure the chip component into position prior to the second alloy reflowing to make the electrical connection.

Over time, IPC (Association Connecting Electronic Industries) studies have turned up some interesting data, ultimately finding that the IPC-SM-782A (1993/1999) was in error on many fronts. As a result, the standard was rewritten and is now known as IPC-7351B (2005/2010) Generic Requirements for Surface Mount Design and Land Pattern Standard. To ensure consistency and stability throughout the production process, an equation designed to calculate the proper pad geometry was included in the document; three acceptable density levels, each based on the component population density of the PCB, also were added.

These important changes all helped to mitigate the tombstone effect. However, the overriding goal is to eliminate this lingering issue altogether, which despite best efforts has remained a significant concern. Until now, despite exhaustive investigative efforts, the cause of chip component tombstoning has remained largely unsolved—and therefore unresolved.

In retrospect, one aspect appears to have been overlooked in the investigation process: the physical component itself. Although physical components may comply with the standard—i.e., the EIA 0402 standard—the physical characteristics of a component must be well understood and eventually ruled out as the culprit.

Root Causes

To test for this, a dimensional comparison was performed on the seven-capacitor and six-resistor component most commonly used by our own customers. The analysis, which examined the component body and its terminations, revealed that six out of seven (86%) capacitors and three out of six (50%) resistor manufacturers utilized different body and termination dimensions and tolerances. This finding is significant.

To validate that discovery, the same comparison was performed using identical component manufacturers with respect to the EIA 0201 and EIA 0603 package type. In all cases, each manufacturer produced an identical part, indicating that EIA 0402 is only one facet to the root cause of the festering tombstone issue.

In light of existing research data, it is now apparent that the tombstone effect is clearly not limited to one root cause. In fact, many factors may have influenced its occurrence over the years. With that understanding, we believed that a proper solution could logically be effected.

To proceed further, it should be noted that three major factors influence tombstoning: component, layout and solder flow behavior. Understanding the relationship between these three factors is critical to ultimately understanding and resolving this important issue.

Note that component equals mass, body/termination size, and associated tolerances; pad geometry equals size/spacing, IPC standard, and CAD library. Additionally, copper exposure equals stencil/solder volume, solder mask clearance/coverage, and solder mask-defined pads verses metal-defined or non-solder mask-defined pads with respect to signal trace and planar connections. Finally, copper density equals solder mask-defined pads verses metal-defined or non-solder mask-defined pads with respect to signal trace and planar connections. Via-in-pad designs and balance also are considered.

Component Differences

While physical component dimensions may differ from manufacturer to manufacturer, and should certainly be considered a part of the ultimate equation, so should the fact that the mass of the component also is a factor: the lower the mass, the more susceptible it is to the influences of solder flow behaviors. EIA 0402 is considered a low-mass component, thus solder flow behaviors must be controlled and implemented from a layout perspective.

It was noted earlier that IPC has rewritten the old IPC-SM-782 standard, resulting in IPC-7351. While this standard appears to have the best layout for EIA 0402s, when the physical body and termination dimensions of components were superimposed onto the IPC-7351-recommended pad geometries it was found that in some cases the recommendation did not accept the component as fabricated. In fact, the pad geometries appeared to have been focused strictly on the nominal component body dimensions and did not take into account other important tolerances.

In contrast, IPC rightly focused strictly on the termination tolerances and variations with regard to part length. The width was found to be in error and only the nominal conditions were stated. This error was uncovered during evaluation of the component manufacturers and should not be disregarded.

Comparitive Equality

For additional clarity in understanding the IPC-7351 standard, the pad geometry is only good for the chosen component. If other manufacturers and components are selected, the physical dimensions must be identical for relevance to be achieved. Any variation in the component when the pad geometry is not designed for that component may result in the dreaded tombstone effect.

Clearly, proper pad geometry is critical in controlling the behavior of the tombstone effect. Since IPC has taken the initiative and rewritten the standard, it is highly logical that the designers’ CAD library might lag in updating that important aspect and that all libraries are therefore suspect to remaining in non-compliance. To ensure critical industry compliance, the validation of compliant pad geometries is ultimately necessary. An EIA 0402-recommended pad geometry was developed to maximize the exposed surface area so that all component variances are accepted while the amount of surface needed to achieve the critical goal is minimized. Our own EIA 0402-recommended pad geometry, as one example, is excellent for multiple components, as typically selected alternates are used on bills of materials.

With a clear understanding of the criticality of a proper pad geometry and its relationship to the EIA 0402 physical component, the focus must shift to solder flow behaviors and their effects on low mass components.

Fig. 2(a) is a released layout for PCB fabrication and CCA. Layers illustrated are copper, solderpaste and soldermask. The soldermask clearance is illustrated at 5 mils beyond the intended (target) pad geometry. Fig. 2(b) is a typical 0402 layout, where one pad (metal defined, or MD) has a connecting trace and the sister pad is soldermask defined (SMD) on either a wide trace or plane. When the PCB is fabricated with respect to process tolerances and controls, the effective surface area for the SMD pad greatly increases from the original intent, as shown in Fig. 2(c). This increased surface area is ~65% larger than the MD sister pad, which has a dramatic effect on the containment of the intended solder volume originally targeted to be the same as the MD pad illustrated in the solderpaste layer. Solder will flow to any exposed copper surface area (Fig. 2(d) and Fig. 2(e). Since the SMD pad is larger than the MD pad, the SMD pad solder volume (height) will be reduced by ~65% compared with the MD pad and its original intent. If the soldermask clearance were to be reduced from 5mils to 2mils, the exposed surface area would only increase by 25%. Although this may provide better control, the aspect of copper density must now be considered.

Copper Density

Copper density is the amount of copper required to heat to a temperature sufficient to reflow solder with respect to a component termination and its target pad. In the simplest approach, this definition is often overlooked or even sacrificed in terms of electrical considerations. However, with respect to low mass components, pad geometry thermal balance is a key factor in the tombstone effect.

Fig. 3(a) and Fig. 3(b) are a released layout for PCB fabrication and CCA. Layers illustrated are copper, solderpaste and soldermask. Soldermask clearance is illustrated at 5 mils beyond the intended (target) pad geometry. Fig. 3(c) is a typical 0402 layout where one pad (MD) has a connecting trace and the sister pad is SMD on either a wide trace or plane. To better understand the amount of copper required, it is necessary to remove the soldermask layer as it does not control heat transfer. When the PCB is sent through the SMT reflow oven, the PCB is believed to heat evenly. From a copper density standpoint with respect to low mass components, this is a wrong assumption.

The MD pad has a much lower copper density compared with the SMD pad. Therefore, the MD pad heats sooner than the SMD pad. In other words, the connecting trace acts as a thermal heat relief to the MD pad, confining the necessary heat to the target pad. Regarding the SMD pad, no thermal heat relief is present; thus, all of the necessary heat for the target pad is sinked away to the plane. With consideration for low mass components, thermal balance for the pad geometry is a key factor. Each pad must be considered as a group and not independently.

Many factors contribute to tombstoning, including component, pad geometry, copper exposure, copper density and solder flow behavior. Balance is essential to solving the low mass component issue:

  • Pad geometry: Must be present for many component manufacturers to be accepted.
  • Layout: Each pad must be treated as a group rather than independently.
  • Copper exposure: Each pad must be nearly equal.
  • Copper density: Each pad must be nearly equal.

Therefore, a three-step approach, where each is used in concert to resolve the tombstone effect, is recommended:

  1. Use optimal EIA 0402-recommended pad geometry in Fig. 4 to provide the best layout solution in order to accept multiple EIA 0402 component manufacturers with a minimal amount of PCB real-estate required.
  2. Set soldermask clearance to 2 mils.
  3. Use a connecting trace between pad and plane—or a very wide trace—equal to the sister pad, as shown in Fig 5.

This investigation successfully resolved an age-old issue that has long lacked resolution. With an understanding of each aspect and their relationships to each other, it is apparent that balance is the key to providing consistency from solder joint to solder joint. The implementation of optimal pad geometry and layout provides a range of benefits, including:

  • The acceptance of multiple EIA 0402 component manufacturers while using only one pad geometry.
  • Use of minimal real-estate.
  • Balanced copper density.
  • Balanced copper exposure.
  • Reduction of the tombstone effect to virtually zero, including associated defects such as PCB damage and missing components.
  • Broadening the layout concept beyond EIA 0402.
  • Improved solder joints regardless of component termination.

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