The size and complexity of system-on-chip (SoC) projects places heavy demands on the design team. One of the more significant aspects of these projects is verification of the system. I recently talked with Adnan Hamid, cofounder and CEO of Breker Verification Systems, about the trends and verification challenges associated with chip design.
Wong: What trends are you seeing in chip design?
Hamid: The sheer size and complexity of today’s system-on-chip (SoC) designs is staggering. Not too long ago, only CPUs, GPUs, and network switches involved really big chips. The integration level of consumer devices has greatly expanded the SoC landscape. Smart phones, tablets, set-top boxes, automobiles, medical devices, and other applications routinely have dozens of embedded processors, hundreds of IP blocks, and millions of gates. Most of these products have short lifetimes before the next generation comes along, so meeting time-to-market requirements and producing a sellable chip on first silicon are critical for commercial success. This puts enormous pressure on every SoC development team.
Wong: What kinds of challenges are designers now facing?
Hamid: These massive SoC designs present challenges throughout the development process, but functional verification is especially challenging. Many studies have shown that verification consumes the largest percentage of resources on SoC projects, so there is a lot of pressure to do more with fewer people in less time. Of course, verification is all about quality and first-silicon success is impossible without a great verification process.
Unfortunately, SoC teams are finding gaps in their verification flow. Testbench simulation techniques such as the Universal Verification Methodology (UVM) standard work well for IP blocks or clusters of blocks, but break down at the full-chip level. Once embedded processors are present, the verification methodology must leverage the power of the processors. Waiting until production software is ready and running it on an in-circuit emulator or an FPGA-based prototype pushes verification too late. In addition to being available only toward the end of a project, production software is inefficient at finding remaining SoC bugs. Verification teams try to plug this gap by hand-writing tests to run on the embedded processors in simulation and emulation, but these are time consuming to develop and not sophisticated.
A similar problem occurs as the SoC validation team brings up an FGPA prototype or the actual silicon delivered from the foundry. Production software rarely boots up right away, and so validation engineers hand-write embedded diagnostics. These are not effective since even experienced programmers have a hard time developing code that exercises many parts of the SoC in parallel. The only answer for both these gaps is automation of the test cases.
Wong: What solutions are available to overcome these challenges?
Hamid: Breker, as an example, offers two closely related commercial products to close the gaps in SoC verification. TrekSoC automatically generates multi-threaded, multi-processor, self-verifying C test cases that run in the SoC’s embedded processors in simulation and simulation acceleration. These test cases stress all aspects of concurrency and coherency in the chip, with more tightly linked parallel threads than could ever be coded by hand. The embedded processors synchronize with appropriate elements of the testbench, including standard UVM verification components. TrekSoC has a visualization technology that shows the real-time progress of all threads running on all processors. TrekSoC also tracks true system coverage in the form of user application scenarios, a high-level metric complementary to other forms of coverage.
TrekSoC-Si (Fig. 1) generates multi-threaded, multi-processor, self-verifying C test cases that run in the SoC’s embedded processors in emulation, FPGA-based prototypes, and production silicon. Since these hardware platforms run much faster than testbench-driven simulation and acceleration, they can stress the design even more thoroughly.
The same visualization and coverage features are available from both TrekSoC and TrekSoC-Si.
Verification engineers can run the test cases on emulators or prototypes while product software is still in development. This speeds up verification and makes it likely that the production software will boot up more quickly since most SoC design bugs will have been found and fixed.
Validation engineers can run generated test cases on the SoC silicon as soon as it comes from the foundry. The organization of the test cases and the power of the visualization make it much easier to detect and address any silicon problems before trying to boot production software.
Both tools generate test cases from the same source: graph-based scenario models that capture the intended behavior of the SoC. These models are intuitive to develop since they capture the data flow of the chip, much like traditional hand-drawn block diagrams. Scenario models capture not just the behavior of individual IP blocks, but the behavior of many blocks strung together into system-level application scenarios representing how the SoC is actually used.
Wong: What differentiates Breker Verification Systems from other verification companies?
Hamid: Breker is focused 100% on SoC verification. The sophistication of the generated test cases is beyond any other solution in the industry, verifying the SoC more effectively. The Breker approach also is efficient, replacing with automation the dozens or even hundreds of engineers hand-writing verification tests and validation diagnostics. These talented embedded programmers can be redeployed to develop applications or other production software. Breker’s graph-based technology has been in use for 10 years on real SoC projects, initially as part of verification consulting services but now productized as TrekSoC and TrekSoC-Si. No other company has Breker’s depth of experience and technology for SoC verification.
Wong: Is there room for more breakthrough technologies? If so, where what part of the design flow?
Hamid: Breker’s success shows that there is indeed room for innovation and creative solutions. Additional breakthrough verification technologies will surely come along. Beyond verification, there are many other SoC development challenges in chip assembly, timing closure, mixed-signal design, and more.
Wong: What advice can you offer readers of Electronic Design?
Hamid: When embarking upon a new SoC project, do not assume that yesterday’s verification solutions will suffice. Many SoC teams have “hit a wall” in their process, resulting in first silicon with serious bugs and the unpleasant choice of performance-limiting software workarounds or a new chip fabrication cycle that will cost millions of dollars and months of product delay. Take a look at the Breker solution before hitting that wall and leverage the power of its generated test cases for a more efficient and more effective SoC verification process to produce first-silicon success.