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These 3 Standards Will Help Foster Smart Low-Power Design

Sept. 17, 2015
As with many aspects of IC design and verification, standards give engineers the ability to describe design intent, move design data through the design flow, and document the final design.
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Karen Bartleson, Senior Director of Community Marketing, Synopsys

Low-power design continues to be one of our industry’s biggest challenges. But with standards, both existing and emerging, design engineers can conceive of and realize their low-power designs throughout the design and implementation process.

One standard for low-power design, IEEE Standard 1801, also known as the Unified Power Format (UPF), has been successfully used for nearly a decade. However, two new standards are emerging that will complement 1801: IEEE P2415 and IEEE P2416. The continuing work on UPF is called P1801; the “P” in front of the numbers indicates that these are all projects underway.

This article explains the purpose of the three standards and how they will work in concert to address the needs of low-power design and verification. It also describes how the leaders of the working groups will ensure that the standards stay within scope, supplement each other, and do not cause inadvertent conflicts. Further, these standards dovetail with the venerable library modeling standard, Liberty, which is discussed later.

The first standard for low-power design is officially called “1801-2013, IEEE Standard for Design and Verification of Low-Power Integrated Circuits.” The year appended to the end of the name shows that it was last updated in 2013. An accompanying errata sheet, published in September 2014, contains two minor edits to the standard that do not affect the standard itself. As mentioned, the standard’s common name is the Unified Power Format, or UPF. It was developed within the standards organization, Accellera, and transferred to the IEEE Standards Association for formal ratification.


UPF is used to describe low-power intent during design implementation, analysis, and verification. The low-power design specification is captured from RTL to GDSII, using a consistent language throughout the entire flow of design and verification. The UPF standard makes it possible for designers to use EDA tools from different vendors as well as in-house specialty tools they can develop themselves.

In a low-power design scheme, the operating voltages of the supply nets are controlled independently, and the networks and design elements connected to them are turned on and off as needed. As a result, the power-supply networks only send power to the areas of the chip that need it, which can significantly reduce the power used by the entire chip. A designer’s low-power design scheme described with the UPF standard includes:

• How each logic design element is supplied power by a power network.

• How each individual supply net should interact with the other ones.

• How to extend logic functionality to the design elements to enable dynamic power switching to each element.

New work is underway on the UPF standard within the IEEE. During this project, the scope of the standard will be expanded to include supporting system-level power models. This will enable integration of IP models smoothly into a system-on-chip (SoC). It also offers an opportunity to make minor updates to the standard. The P1801 project is authorized to continue through the end of 2017.


The second project in the low-power standards space is officially called “P2415 - Standard for Unified Hardware Abstraction and Layer for Energy Proportional Electronic Systems.” Though it’s authorized until the end of 2018, it can be extended under the right circumstances in IEEE projects. P2415 complements P1801 to address a higher-level power-management challenge.

Think about P1801 as the format to describe power intent by the hardware design engineer looking inside the SoC. The P2415 standard addresses the corresponding problem of representing the hardware’s power-management capabilities to the software architect looking at the hardware from outside. Some call P1801 as a “hardware in” and P2415 as a “hardware out” power-format standard.

Both working groups for P1801 and P2415 are working together to ensure the alignment needed for energy-efficient systems design. The emerging P2415 standard is compatible with the current and future IEEE 1801 UPF standard to support an integrated design flow. It provides a higher level of abstraction and therefore enables earlier (more abstract) modeling of power states using UPF. In addition, the new standard complements functional models in VHDL, Verilog, SystemVerilog, and/or SystemC by providing an abstraction of the design hierarchy as well as an abstraction of the design behavior with regard to power and energy usage.

The new P2415 standard defines the syntax and semantics for an energy-oriented description of hardware, software, and power management for electronic systems. It enables specifying, modeling, verifying, designing, managing, testing, and measuring the energy features of the device, covering both the pre- and post-silicon design flow.

On the hardware side, the P2415 description covers enumeration of semiconductor intellectual-property components (SoC, board, device): memory map, bus structure, interrupt logic, clock and reset tree, operating states and points, state transitions, plus energy and power attributes. On the software side, the description covers software activities and events, scenarios, external influences (including user input), and operational constraints. On the power-management side, the description covers activity-dependent energy control.


The third active standards project for low-power standards is P2416. It is a “Standard for Power Modeling to Enable System Level Analysis.” Like P2415, the project is authorized through the end of 2018. It, too, is a standard that complements others in the low-power design space. Its focus is on power models themselves, in support of standards that describe low-power design intent.

At each stage in the design process, the need arises for power models that represent appropriate abstraction and accuracy. The P2416 working group recognizes such need and is working toward a meta-model standard focused on parameterization and abstraction. This will enable system, software, and hardware IP-centric power analysis and optimization.

The standard will define concepts for the development of parameterized, accurate, efficient, and complete power models for systems and hardware IP blocks that are usable for system power analysis and optimization. Such models suit software-development flows and hardware-design flows, as well as represent both pre-silicon estimated and post-silicon measured data.

P2416 will also define the necessary requirements for the information content of parameterized, accurate, efficient, and complete power models. These requirements help guide development and usage of other related power, workload, and functional modeling standards, such as IEEE Standard P1801 - UPF, IEEE Standard 1666 - SystemC, and IEEE Standard 1800 - SystemVerilog. Beyond defining the concepts and related standard requirements, the proposed specification recommends the use of other relevant design flow standards (e.g., IP-XACT, which is an XML format that defines and describes electronic components and their designs) with the objective of enabling more complete and usable power-aware design flows.

It’s important to note that P2416 is not a replacement for the Liberty library modeling standard. Liberty is the long-time, broadly adopted standard for the lowest-level models used by hardware designers to map their designs from high-level functional descriptions to gates. Although Liberty’s original modeling features only captured functional and timing information, continuous enhancements have enabled the models to capture information for test, manufacturability, and power. Recent enhancements in the low-power arena include modeling of low-power process parameters, such as variability, and of special cells to support advanced power-management techniques.

Noteworthy is that three standards-developing organizations are cooperating in the projects for the three standards. The IEEE Standards Association, Accellera, and Si2 held a joint workshop at the 2015 Design Automation Conference, at which participants discussed the need and direction for low-power design standards. The IEEE Standards Association’s Design Automation Standards Committee (DASC) is operating as an ad-hoc committee of the leaders of the three projects’ working groups to ensure that the efforts remain aligned. According to The Ten Commandments for Effective Standards, this is a perfect example of the corollary to the first “commandment”: Establish a cooperative standards environment.

These three projects for low-power design standards are open to participation by any and all interested parties. More specifically, they would welcome it. To learn more about the projects and find out how to participate, visit the working groups’ websites and contact the liaison for the project:

• P1801: https://standards.ieee.org/develop/wg/UPF.html

• P2415: https://standards.ieee.org/develop/wg/UHA.html

• P2416: https://standards.ieee.org/develop/wg/System_Level_Power_Modeling.html


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