The combination of increased layout data to check, coupled with increased rules, and complexity of rules to check, puts a heavy toll on the ability of chip designers to complete physical verification and meet tape-out windows. In this paper, you will learn:

• How Moore’s law directly impacts DRC computational requirements
• How to ensure use of accurate and optimized rule files
• Best practices for layout fill generation
• How to extract the most efficiency and scaling from multi-processor distributed compute farms.