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Dual-Threaded DSP Targets AI and Wireless Apps

May 2, 2025

The Ceva-XC23 DSP core has two independent execution threads and a dynamic scheduled vector-processor.

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The Ceva-XC23 DSP core from Ceva is built to handle artificial-intelligence (AI) applications as well as RF chores for 45, 5G, and 5G-Advanced NR applicions. It delivers 5.14 CoreMark/MHz with easy integration via AMBA4 buses.

1. The Ceva-XC23 DSP incorporates a pair of processing elements with a shared vector computation unit (VCU).

The dual processing elements feature L1 cache in addition to processing and data tightly coupled memory (PTCM/DTCM). The individual scalar execution units are augmented with a shared, 512-bit, SIMD vector computation unit (VCU). This includes 128 16-bit MACs. Nine-issue VLIW architecture is supported by an optimizing LLVM C compiler.

The processing system is designed to take on AI applications with support for INT8/16/32 data types plus half-, single-, and double-precision floating point. There is dedicated 5G/5G-Advanced instructions to improve 5G NR acceleration.

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