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DSP Handles AI-Driven Communication Tasks

May 20, 2025

The Ceva-XC21/XC23 dual core targets wireless infrastructure applications.

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Ceva's dual DSP core targets real-time applications with an artificial intelligence (AI) bent (see figure). The Ceva-XC21/XC23 cores incorporate two DSP engines and a share vector unit.

The Ceva-X23 sports dual DSP cores and a vector unit designed to handle AI chores.

The Ceva-XC23 DSP has a smaller footprint and delivers 2.4X the performance (5.14 CoreMark/MHz) of the company's previous-generation Ceva-XC architecture. It can handle 4G, 5G, and 5G-Advanced NR chores, including supporting ultra-reliable, low-latency communication (uRLLC), while providing AI support.

The contention-free multithread, dual-core DSP is augmented by a 512-bit, SIMD vector unit. The 128 16-bit MACs support INT8/16/32 data types as well as half, single, and double precision floating-point values. The DSP employs a nine-issue VLIW instruction-set architecture supported by an optimizing LLVM C compiler.

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