Infineon Technologies has fabricated functional silicon-carbide (SiC) power devices on 300-mm wafers at its Villach, Austria, semiconductor plant. The company reports using existing silicon-processing equipment, demonstrating the feasibility of processing larger SiC substrates in an established semiconductor fabrication facility.

The announcement concerns two manufacturing developments: fabricating power devices on 300-mm SiC substrates and using a laser-based technique to separate wafers from SiC crystals without conventional wire sawing.

Infineon hasn't disclosed device specifications, electrical test results, manufacturing yields, or a timetable for volume production.

Larger Wafers Present Processing Challenges

Most commercial SiC power semiconductors have historically been manufactured on 150-mm wafers, with manufacturers transitioning to 200-mm substrates.

A 300-mm wafer has 2.25X the surface area of a 200-mm wafer — approximately 70,686 mm² versus 31,416 mm² — potentially enabling more devices to be fabricated during each processing cycle.

The actual number of usable devices depends on die dimensions, edge exclusions, defect densities, and manufacturing yield.

Silicon carbide is substantially harder than silicon and has different mechanical and thermal properties. Manufacturing challenges include maintaining wafer flatness, controlling residual stress, and preserving consistent material properties across a larger substrate.

Defects originating during crystal growth can also affect device yield. Threading dislocations, basal-plane dislocations, and other crystallographic imperfections may influence device electrical characteristics and reliability.

Larger substrates must remain mechanically stable through lithography, implantation, thermal processing, and metallization. Variations in process conditions across a wafer could also produce differences in device characteristics.

For SiC MOSFETs, relevant measurements include breakdown voltage, threshold voltage, drain-source on-resistance, gate leakage, and off-state drain leakage.

Infineon hasn't provided wafer maps or statistical distributions for these parameters.

Adapting Existing Silicon Fabrication Equipment

Using established 300-mm silicon equipment could reduce the capital investment required for some fabrication operations. However, equipment designed for silicon processing isn't necessarily capable of performing every SiC manufacturing step without modification.

SiC devices typically require ion implantation followed by high-temperature annealing to activate the implanted dopants. Activation temperatures commonly approach or exceed 1,600°C, substantially above those used in typical silicon CMOS processing.

For SiC MOSFETs, gate-oxide formation also requires careful control. Defects at the SiC/silicon-dioxide interface can trap charge, reduce channel mobility, and influence threshold-voltage stability.

Maintaining uniform electrical characteristics across 300 mm requires control of these processes across the larger substrate.

Infineon hasn't specified which existing silicon tools were used, what modifications were required, or which process steps relied on specialized SiC equipment.

Replacing Wire Sawing with Laser-Based Separation

The company also reports feasibility testing of its Cold Split process on 300-mm SiC material at its Dresden, Germany, facility.

The process was developed by Siltectra, which Infineon acquired in 2018.

Conventional SiC wafer production uses diamond-wire saws to cut individual wafers from a cylindrical single-crystal boule. The material removed by the wire becomes kerf loss and can't be incorporated into the resulting substrates.

The laser-based approach creates a controlled subsurface damage layer within the crystal. A polymer layer is applied, and temperature-induced mechanical stress helps propagate a fracture along the laser-modified plane, separating a wafer from the remaining crystal.

The separated wafer requires subsequent surface finishing before device fabrication.

The technique can reduce material consumed during separation, although grinding, polishing, and process-related damage still affect usable-wafer yield.

Infineon reports feasibility at 300 mm but hasn't disclosed quantitative measurements of material recovery, finished-wafer yield, surface roughness, or process throughput.

Rayton Takes a Particle-Accelerator Approach

California-based Rayton [editor disclosure: I'm a small crowdfund investor, which is how I know about the technology], founded in 2013, developed an alternative approach for producing thin semiconductor substrates without conventional wire sawing. Rather than utilizing a laser to create a fracture plane, Rayton uses a particle accelerator to implant protons at a controlled depth beneath a crystal's surface.

The implanted hydrogen ions create a buried damaged region that facilitates separation during subsequent thermal processing. The implanted surface is bonded to a carrier substrate before annealing, allowing a thin semiconductor layer to separate from the donor crystal while remaining attached to the carrier.

Originally developed for thin silicon photovoltaic wafers, Rayton's approach was subsequently directed toward compound semiconductors, including gallium arsenide, gallium nitride, and SiC. The company worked with Phoenix Nuclear Labs on proton-implantation equipment.

Both approaches seek to reduce the consumption of expensive semiconductor crystal material. Rayton's technique targets thin transferred layers, whereas Infineon's laser-based process can separate thicker, self-supporting wafers.

Rayton's development doesn't establish commercial-scale SiC substrate production, and the two companies haven't published directly comparable manufacturing cost or yield data.

Implications for Power Electronics

SiC's wide bandgap and high critical electric field enable high-voltage devices with thinner, more heavily doped drift regions than comparable silicon devices.

These characteristics can reduce conduction resistance and support fast-switching power devices used in electric-vehicle traction inverters, charging systems, industrial motor drives, renewable-energy converters, and high-power supplies.

Increasing wafer diameter doesn't directly improve device electrical characteristics. The potential advantage lies in manufacturing throughput and the cost per acceptable device.

Infineon continues to develop its 200-mm SiC manufacturing operations and hasn't announced a date for 300-mm volume production.

Assessing the commercial significance of the demonstration will require electrical characterization across multiple wafers, manufacturing yield data, reliability qualification, and comparisons of production costs with established substrate sizes.

For now, the company has demonstrated functional SiC power-device fabrication on 300-mm wafers and feasibility of laser-based separation at that diameter. Neither announcement establishes production yields or lower finished-device costs.

Infineon will display a processed wafer at electronica 2026, November 10–13, in Hall C3, Booth 502, at Messe München in Munich, Germany.

Source: Infineon press release, November 9, 2026.