NPU is Built Around RISC-V Core
What you'll learn:
- What is the MIPS S8200 NPU?
- How does RISC-V fit in the NPU architecture?
MIPS, now part of GlobalFoundries, builds on its legacy of high-performance, power-efficient processor cores. One of the latest is the MIPS S8200 neural processing unit (NPU) IP that’s built on a RISC-V vector processing CPU. The platform has been augmented to support artificial-intelligence/machine-learning (AI/ML) models including large language models (LLMs). I talked with James Prior, Marketing Manager at MIPS/GlobalFoundries, about the MIPS S8200 (watch the video above).
MIPS has moved into the RISC-V space in a big way. The MIPS P8700 six-core cluster can be replicated up to 64 times to handle up to 768 threads. The MIPS S8200 can also be replicated to support larger AI/ML models as well as handle multiple models simultaneously. When configured with tightly coupled memory, the IP is able to take on a range of vector and matrix applications.
The architecture scales from tens of TOPS to thousands of TOPS. These are two components of MIPS’ Sense, Think, Act and Communicate architecture approach, where each is based on different RISC-V configurations optimized for those function areas. The S8200 fits under the Think category.
MIPS provides development software that allows AI/ML models from popular frameworks like PyTorch and TensorFlow to be compiled for the S8200. There’s also a virtual, online digital twin that can be used to optimize a design.
>>Check out more of our CES 2026 coverage, and the TechXchange for articles and videos on RISC-V
About the Author
William G. Wong
Senior Content Director - Electronic Design and Microwaves & RF
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I earned a Bachelor of Electrical Engineering at the Georgia Institute of Technology and a Masters in Computer Science from Rutgers University. I still do a bit of programming using everything from C and C++ to Rust and Ada/SPARK. I do a bit of PHP programming for Drupal websites. I have posted a few Drupal modules.
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