Intel is increasing the competitive pressure on AMD’s Xilinx with plans to start selling smaller-form-factor FPGAs targeting industrial, automotive, communications, consumer, medical devices, and other markets where power efficiency takes priority over speed.
The Santa Clara, California-based company plans to expand its Agilex family of FPGAs with a new chip for edge and embedded systems code-named “Sundance Mesa.” It will supply more than 60% more performance per watt than AMD’s Xilinx chips when it rolls out to market next year, according to the company.
Field-programmable gate arrays (FPGAs) are special-purpose chips that can be reconfigured at any time to adapt them to specific workloads or future-proof them for new industry standards. This allows the chips to run those workloads more efficiently than a standard CPU that’s more general-purpose in nature. FPGAs also have much more flexibility than ASICs, which are chips custom-built for specific processing jobs.
In a briefing ahead of its Innovation event, Intel revealed a new roadmap for the product line that includes mid-range Agilex FPGAs for the edge and embedded markets, where it’s necessary to process data locally to keep system-level latency in check and save power that’s at a premium on the edge. The new chips will replace its Cyclone, Arria, and Stratix FPGAs based on 20-, 28-nm, and other aging process nodes.
While it has struggled to remain competitive with Xilinx in recent years, executives at the U.S. chipmaker have promised it is ready to become a stronger competitor to AMD, which acquired FPGA giant Xilinx for $49 billion at the start of the year.
“This is something of a coming out party,” said Shannon Poulin, a longtime Intel executive whom CEO Pat Gelsinger promoted last year to take over the programmable solutions group (PSG).
All Part of the Plan
Intel is racing to regain its footing as the unquestioned leader in chip manufacturing. Gelsinger in 2021 set out an aggressive roadmap that sees it releasing a new generation of process technology every year from 2021 to 2025.
Poulin said that one of the parts of his plan is to bring Intel’s programmable chips even closer to the front of the line for the most advanced process technologies at its revitalized foundry services business—IFS.
“We still have many of our products on legacy supply nodes,” he pointed out, “and many of those nodes are not made at Intel. And I’m talking about nodes that are five, ten, even twenty years old in some cases.”
“We’re moving our whole portfolio over to Intel manufacturing,” he added.
He’s keen to put Intel’s programmable solutions in the priority lane because FPGAs are taking on a bigger role in a wide range of markets from aerospace and defense to industrial and automotive to 5G networks.
“We’re seeing our customers move at a different pace—not at the pace of hardware but at a programmable, software-like pace,” Poulin told Electronic Design. “That is causing them to take another look at FPGAs that are reconfigurable and programmable. They’re investing in platforms because they can innovate at a faster pace than they could if they were going [to design] fixed hardware. And in some cases, they are innovating in different ways than they would need to if they were going to simply change software on fixed hardware.”
They are also becoming widely used by cloud-computing leaders, such as Amazon, Google, and Microsoft, to run networking, security, storage, and even machine-learning workloads in servers faster and for less power.
To tap into the booming data-center and other markets, Intel is investing aggressively in the high end of its Agilex family of FPGAs, which are packed with high-density programmable logic tightly woven into a fabric.
The company rolled out the high-performance Stratix 10 FPGAs based on its 14-nm node in 2018 and introduced the first devices in the Agilex family, the F-Series and I-Series, built on its 10-nm process technology in 2019.
It's pushing the envelope even further with the Agilex M-Series, which is based on the Intel 7 node (what the company calls its enhanced 10-nm “SuperFin” transistor technology) and comes co-packaged with high-bandwidth memory (HBM). While it announced the M-Series early this year, Intel plans to release the product family in 2023 or 2024.
The high-end chips consist of chiplets (or tiles) linked together using Intel’s 2.5D advanced packaging technology called EMIB. A central tile loaded with the FPGA’s programmable logic is surrounded by I/O tiles with Ethernet ports and SerDes for PCIe and Compute Express Link (CXL) interfaces, or memory tiles. While advanced packaging gives Intel more flexibility and performance, it’s a costly and power-hungry approach.
Hard and Soft Logic
While Poulin also plans to upgrade its high-end, chiplet-based Agilex FPGA family as part of the roadmap, in the future he’s keen to become a stronger competitor to Xilinx on more than the high-performance front.
Intel said that while Sundance will feature a fraction of the programmable logic elements (LE)—on the order of 50,000—at the heart of its high-end FPGAs, it comes packed in a more power-efficient, single-chip configuration.
According to the company, the programmable chip is based on the same Intel 7 process as its high-end, memory-heavy Agilex M-series FPGA, offering 1.6X better performance per watt than Xilinx’s rival 16-nm Artix UltraScale+ SoCs.
The new Agilex family inherits many of the most important architectural features of its previous Agilex devices, including a new generation of Intel’s “HyperFlex” programmable logic technology. The HyperFlex architecture adds a host of "hyper-registers" to facilitate pipelining of data through the FPGA connection fabric. These units prevent the pipelines inside the chip from becoming clogged, improving its throughput.
The Sundance family also incorporates a new hard processor system (HPS), which consists of a dual-core Arm Cortex-A76 CPU clocked at up to 1.8 GHz and dual-core Cortex-A55 CPU at 1.5 GHz. The CPU cores can be coupled using Arm’s DynamIQ technology, which melds the Cortex-A76 and Cortex-A55 into a larger app processor cluster to help offer improved power and performance for edge devices equipped with the FPGA.
The chips will also incorporate an upgraded version of the digital-signal-processing (DSP) block in its previous Agilex FPGAs to offer better AI computational features, as well as areas such as image and video processing.
Also integrated are hard IP cores for time-sensitive networking (TSN) to reduce delays in industrial networks, as well as the MIPI D-PHY interface for video processing, plus support for the PCIe Gen 4 protocol.
On top of that, the new chips will be equipped with hard memory controllers for DDR4, LPDDR4, DDR5, and LPDDR5 DRAM; Ethernet, USB ports; general-purpose IOs; cryptography engines; and 28-GB/s transceivers.
Mid-Range in Range
In addition to the Sundance FPGA, executives said Intel is also adding the mid-range Agilex D-Series to the programmable chip family, which will contain on the order of 100,000 programmable logic gates based on Intel 7.
Intel said the D-Series FPGAs, which will likely target many of the same communications, industrial, and robotics markets as its Xeon D SoCs, will have 2X better fabric performance per watt than rival 7-nm FPGAs. The initial chips will sample in 2023, with volume shipments starting in 2024.
The company’s plan to bring its Agilex family into the future signals that it continues to see FPGAs as an important part of its future. Intel said that the roadmap for its Agilex family of FPGAs extends to 2025.
“There is a lot of work we’re doing behind the scenes to build a robust portfolio of products,” said Poulin.