Synopsys is already one of the world’s largest suppliers of chip design software. But its plans to buy Ansys in a $35 billion cash-and-stock deal will create a more formidable player in the broader realm of electronic design and engineering software.
The deal will bring together Synopsys’ electronic design automation (EDA) tools that virtually every major player in the semiconductor industry uses to design chips with Ansys’ broad lineup of electronic simulation and analysis tools. Ansys is primarily a purveyor of system-level software that can simulate and evaluate the electronic systems that house these chips. Ansys is firmly established in industries such as aerospace, defense, automotive, energy, and industrial.
Given the complexity of today's intelligent systems, it makes sense to integrate chip design and simulation and analysis to ensure everything under the hood of a system functions properly in a real-world setting.
Synopsys said the prospect of catering to all of the different engineers who have a hand in any given electronic product was a driving force behind the deal. “Bringing together Synopsys industry-leading EDA solutions along with Ansys' world-class simulation and analysis capabilities will enable us to deliver a holistic, powerful, and seamlessly integrated silicon to systems approach to innovation,” said Synopsys CEO Sassine Ghazi.
Synopsys is paying a hefty premium to buy Ansys, signaling the importance of Ansys’ system-level analysis and simulation tools to its “silicon-to-systems” strategy. Under the terms of the agreement, Ansys’ shareholders will get $197.00 in cash and 0.3450 shares of Synopsys stock for every share, valuing Ansys at about $35 billion. The deal represents a 29% premium over Ansys' last closing stock price, according to the companies.
The tie-up also has the potential to strengthen its competitive footing against rivals, namely Cadence Design Systems and Siemens EDA. Synopsys indicated that the deal is anticipated to close in the first half of 2025.
Synopsys: From EDA to Engineering Software Giant?
Designing a modern chip is a complex three-dimensional problem that can take even highly skilled engineers using EDA software tools from the likes of Synopsys several years and hundreds of millions of dollars to solve. As Moore’s Law runs out of road, building a state-of-the-art processor or other chip is becoming even more challenging and costly. Innovations will continue in semiconductor processes and even in the transistors (the nanosheet) and interconnects (backside power delivery). But taking advantage of them is an increasingly daunting task.
To achieve the best balance of power, performance, area, and cost (PPAC), it’s not enough for engineers to build a chip by themselves and then bring the blueprints to a foundry to be manufactured. Instead, it’s vital to work closely with foundries to fine-tune the chip design—the logic cells and various other building blocks—and the process technology it uses in tandem, a practice called design-technology co-optimization (DTCO).
But as the semiconductor industry falls further behind on Moore’s Law, engineers need to evaluate more than just the relationship between chip design and process tech. Enter system-technology co-optimization (STCO).
STCO as a philosophy stands out because it requires you to take everything about a system into account—from the applications, workloads, and software that it supports, to the IP built into the silicon and the type of chips placed inside the package, and finally to the manufacturing process itself. In between, it requires engineers to examine the system architecture, too. All of these building blocks are optimized together for the best result.
The concept is also taking off as AMD, Intel, and other semiconductor firms start breaking up systems-on-chip (SoCs) into smaller functional die called chiplets and reassembling them in single system-in-package (SiP) using 3D stacking and other types of advanced packaging technology. That means a single, overly complicated chip can be “disaggregated” into its core functions that are each placed on a separate chiplet. Each silicon die can then be made using the best semiconductor process technology for the job and at any foundry you want.
Synopsys is upgrading its EDA tools with artificial intelligence (AI) and other innovations to help navigate these challenges at the chip level. However, acquiring Ansys would give it a broader, tightly integrated package of software that covers up to full systems.
Ansys brings to the table simulation and other software used by researchers, engineers, and chip designers to analyze full products and systems where chips end up. Among the company's main rivals are Autodesk (with its Fusion 360 platform) and Dassault Systèmes (with its SolidWorks software). After it folds the company's tools into its core EDA software, Synopsys will be able to offer a more complete software suite for designing systems inside and out.
Integrating these tools will also enable mutual customers to investigate the impacts of the chip’s design at a package and system level—and vice versa—further ahead of time, as well as spot potential areas of improvement.
This integration will be useful when Synopsys works more closely with non-traditional customers, including auto OEMs such as Ford and GM, and tech giants such as Amazon, Google, and Microsoft. They’re all bringing more chip design efforts in-house.
Uniting Everything from Silicon to System Design
Synopsys said the tie-up of its electronic design software with the system-level simulation and analysis tools from Ansys will be a boon to its semiconductor customers, which are dealing with lots of difficulties.
But the company said all Ansys customers, including those outside the semiconductor industry, stand to benefit, too, since they will be able to gain more valuable insights into the electronics at the heart of their systems.
Following the Ansys deal, Synopsys said it would see its total addressable market (TAM) expand by 50% rising to about $28 billion per year, and the merged company’s annual revenue rising to approximately $8 billion.
Ghazi explained that the deal is “the logical next step” for both companies, which have had a long-term partnership in place for more than half a decade. Under the pact, Synopsys and Ansys teamed up to tightly integrate their electronic design, simulation, and analysis tools in such a way that mutual customers can test chips used in the mobile, automotive, and high-performance computing markets against quality and reliability standards.
To help engineers pinpoint potential mistakes further ahead of time, the companies integrated Ansys’ power integrity and reliability sign-off technologies with Synopsys physical implementation tools for “in-design” use.
As a unified company, Synopsys and Ansys can more tightly integrate a wider range of software tools, in a way that helps customers roll out high-performance, reliable products faster while curtailing power, die area, and cost.
“This transformative combination brings together each company's highly complementary capabilities to meet the evolving needs of today's engineers and give them unprecedented insight into the performance of their products,” said Ansys CEO Ajei Gopal.
He added, “The combined company will accelerate the development of our joint portfolio and deliver an increased level of innovation, which will benefit Ansys' traditional customers.”
The new company plans to make approximately $400 million more revenue per year than Synopsys and Ansys could by themselves by the fourth year after the deal, rising to more than $1 billion a year over the long term.
On top of that, Synopsys said it sees the potential for $400 million of combined cost savings by the third year.