According to Microchip Technology, it’s launched the world’s first 3-nm PCIe Gen 6 switch with the Switchtec Gen 6 PCIe Fanout Switch Family, which is designed to power modern AI, HPC, and hyperscale data centers. The switches in the family offer double the bandwidth of PCIe 5.0 — up to 64 GT/s per lane — while providing 160 lanes of connectivity, lower latency, and reduced power consumption.
Built on the 3-nm process, they serve as a significant leap in performance and efficiency for next-gen compute architectures.
The switches also incorporate post-quantum safe cryptography, secure boot, and a hardware root of trust, meeting the CNSA 2.0 standard to ensure data integrity, in addition to Support for Flow Control Unit (FLIT) mode and forward error correction (FEC). As a result, they’re well-suited for AI and data analytics workloads.
Each Switchtec Gen 6 device features 20 ports and 10 stacks, along with hot-plug and surprise-plug controllers, non-transparent bridging (NTB) for multiple host domains, and multicast capabilities. A built-in MIPS processor enables advanced diagnostics, error containment, and dynamic bifurcation at x8 and x16 configurations.
"Rapid innovation in the AI era is prompting data center architectures to move away from traditional designs and shift to a model where components are organized as a pool of shared resources," said Brian McCarson, VP of Microchip's data center solutions business unit. "By expanding our proven Switchtec product line to PCIe 6.0, we're enabling this transformation with technology that facilitates direct communication between critical compute resources and delivers the most powerful and energy-efficient switch we've ever produced."
According to Microchip, developers can use ChipLink diagnostic tools via an intuitive GUI for configuration, debugging, and performance analysis, while the PM61160-KIT evaluation board provides hands-on testing for system architects. Samples of the Switchtec Gen 6 PCIe switches are now available to qualified customers.
