Megagate/Megabit Platform ASICs Add Fuel To Serial-Transfer Speeds

March 31, 2005
The Xtreme2 series RapidChip platform ASICs stack up the specs. These LSI Logic chips deliver up to 48 serializer/deserializer (SERDES) ports that achieve up to 4.25-Gbit/s data-transfer rates. They also provide a maximum of 5 million usable gates

The Xtreme2 series RapidChip platform ASICs stack up the specs. These LSI Logic chips deliver up to 48 serializer/deserializer (SERDES) ports that achieve up to 4.25-Gbit/s data-transfer rates. They also provide a maximum of 5 million usable gates and 3.7 Mbits of configurable static RAM.

Xtreme2 masterslices support popular external high-bandwidth memory interfaces like DDR2 and QDR. The chips' internal SRAM is based on the company's MatrixRAM architecture. As such, designers can implement more memory instances within the SRAM blocks than in any other company's configurable memory structures.

The MatrixRAM pre-diffused memory building blocks can be used individually or combined to form larger memories. Consequently, the memories can conform to any application's requirements, whether wide, narrow, shallow, or deep. Instances are densely packed and pre-diffused, so routing overhead is low and the resulting memories are extremely fast (300 MHz).

The Xtreme2 series packs up to 48 of LSI Logic's GigaBlaze and Hydra SERDES. Each of the initial dozen masterslices contains four phase-locked loops and a different combination of GigaBlaze and Hydra SERDES to satisfy a range of applications across multiple markets. The SERDES can support Gigabit Ethernet, 10 Gigabit Ethernet (XAUI), PCI Express (including ASI), Fibre Channel, InfiniBand, CX4, Serial RIO, SGMII, SPI4.2, SPI5, SAS, SATA, HyperTransport, and other serial interfaces.

Along with the SERDES ports, additional I/O pads support a wide range of high-speed, low-latency parallel memory interfaces—DDR2, RLDRAM2, FCRAM2, and QDR. Fast low-voltage differential-signaling interfaces such as SPI4.2 are supported as well. The I/O cells include on-die termination, slew-rate control, and source-impedance control to ensure good signal integrity at data rates reaching 1 Gbit/s.

Predefined sites called "landing zones" can hold an ARM processor (an ARM966 or ARM1156 core) or memory to support the SERDES ports. An extensive portfolio of proven intellectual property offers cores and tools from LSI Logic and third parties via RapidChip's Platform ASIC Partner Program.

The smallest of the Xtreme2 slices, the RC11XT622, packs between 1.6 and 2.2 Mgates, 1.3 Mbits of RAM, eight GigaBlaze SERDES ports, and up to 510 configurable I/O pads. The largest, the RC11XT776, holds between 4.5 and 5.4 Mgates, 3.8 Mbits of RAM, 40 Hydra SERDES ports, and up to 578 I/O pads.

In 25,000-unit lots, prices in 2006 will range from about $80 each for the XT622 to $185 each for the XT776.

LSI Logic Corp. www.lsilogic.com (408) 433-8000
About the Author

Dave Bursky | Technologist

Dave Bursky, the founder of New Ideas in Communications, a publication website featuring the blog column Chipnastics – the Art and Science of Chip Design. He is also president of PRN Engineering, a technical writing and market consulting company. Prior to these organizations, he spent about a dozen years as a contributing editor to Chip Design magazine. Concurrent with Chip Design, he was also the technical editorial manager at Maxim Integrated Products, and prior to Maxim, Dave spent over 35 years working as an engineer for the U.S. Army Electronics Command and an editor with Electronic Design Magazine.

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