ASIC OptionsSponsored by: LSI LOGIC CORP.

Sept. 6, 2004
Evaluate ASIC Vendor Resources To Select The Best ASIC Solution

Each new ASIC process generation doubles to quadruples the complexity of chips you can design versus the previous generation process. That higher complexity of today brings more complex design challenges and the increasing need to leverage available intellectual property (IP) to reduce the design time.

In many ways, crafting an ASIC is like creating a commodity yet gourmet hamburger (Fig. 1). You start with basic building blocks—silicon (hamburger), logic cells (lettuce and tomato), and then add specialty IP (pickles, bacon, cheese, etc.), unique IP (special sauce), and a package (bun). However, just as in the food realm, the quality of the result often depends on the quality of the ingredients, so to get the best results, you have to check out all aspects of the design chain, just as a good chef will test and sample all the ingredients from various suppliers prior to cooking.

Whether it's a field-programmable gate array (FPGA), platform ASIC, or standard-cell ASIC, the physical design issues associated with the smaller geometries grow more difficult, the tools get more complicated to deal with parameters that previously could be ignored, and the amount of functionality being incorporated on the IC explodes. Extensive and effective use of IP is one primary technique to combat this compounding complexity. Properly productized IP blocks have the ability to shield the physical issues, mitigate the tool complexity, and drastically reduce the amount of functionality that the engineering teams must design and validate.

When starting a design, hooking up with an ASIC partner early in the logic design process can provide many benefits over waiting until the logic design is done before selecting a vendor to work with. One of the main benefits of starting early with a partner is early access to the breadth of IP available from that vendor as well as from its various partners. Additionally, the IP portfolio deliverables are compliant with the tool flows used by the vendor and the IP blocks are often "tuned" for optimal performance in the specific processes offered by the vendor.

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