Clock Dividers Keep Jitter, Skew To A Minimum

July 21, 2003

A series of six high-speed programmable clock drivers, available with LVPECL or low-voltage differential signaling (LVDS) interfaces, meets the ultra-low jitter and skew requirements of Sonet/synchronous-digital-hierarchy communications and other high-performance systems. The SY89871/2/3/4/5/6 include a patent-pending input stage with internal termination and the ability to accept any differential input source. Skew within the devices is kept to less than 15 ps, while signal rise and fall times are less than 250 ps. Jitter is kept to less than 10 ps p-p over temperature and voltage. Programmable divide ratios include 1, 2, 4, 8, or 16. Devices come housed in 3- by 3-mm, 16-contact micro-lead-frame surface-mount packages. Prices start at $4.40 apiece in lots of 1000 units.

Micrel Semiconductorwww.micrel.com; (408) 914-7765

About the Author

Dave Bursky

Technologist

Dave Bursky, the founder of New Ideas in Communications, a publication website featuring the blog column Chipnastics – the Art and Science of Chip Design. He is also president of PRN Engineering, a technical writing and market consulting company. Prior to these organizations, he spent about a dozen years as a contributing editor to Chip Design magazine. Concurrent with Chip Design, he was also the technical editorial manager at Maxim Integrated Products, and prior to Maxim, Dave spent over 35 years working as an engineer for the U.S. Army Electronics Command and an editor with Electronic Design Magazine.