In-System PLDs Come Loaded With 1024 Logic Cells, 512 kbits Of RAM

Sept. 1, 2003

Two new members of the ispXPLD expanded programmable logic family, the ispXPLD5256MX and 51024MX, come with 256 and 1024 logic cells, respectively. The 5256MX also packs 128 kbits of on-chip memory, while the 51024MX includes 512 kbits of on-chip RAM. With a top operating speed of 300 MHz, the 5256MX offers pin-to-pin delays of 4.0 ns (t_pd), 2.8 ns (t_cko), and 2.2 ns (t_s). The 51024MX features a top clock speed of 235 MHz and pin-to-pin delays of 5.2 ns (t_pd), 3.8 ns (t_cko), and 3 ns (t_s). The 5256MX comes in a 256-contact fine-pitch BGA package, while the 51024MX is housed in either a 484- or 672-contact fine-pitch BGA package. In lots of 10,000 units, the 5256MX and 51024MX cost $9.50 and $42 each, respectively.

Lattice Semiconductor Corpwww.latticesemi.com; (503) 268-8000

About the Author

Dave Bursky

Technologist

Dave Bursky, the founder of New Ideas in Communications, a publication website featuring the blog column Chipnastics – the Art and Science of Chip Design. He is also president of PRN Engineering, a technical writing and market consulting company. Prior to these organizations, he spent about a dozen years as a contributing editor to Chip Design magazine. Concurrent with Chip Design, he was also the technical editorial manager at Maxim Integrated Products, and prior to Maxim, Dave spent over 35 years working as an engineer for the U.S. Army Electronics Command and an editor with Electronic Design Magazine.