Improved Target Designs Promise Easier Chip-Feature Measurement

May 28, 2007
Measuring the relative positions of chip features on ever-denser devices could soon become a whole lot easier.

As the sizes of features squeezed onto silicon chips shrink ever smaller, the task of measuring their relative positions becomes increasingly challenging -- and costly -- for chipmakers. Yet the answer to measuring ever-tinier chip features might not lie in expensive new equipment, claims Rick Silver, a high-resolution objects metrology physicist at the National Institute of Standards and Technology (NIST) in Gaithersburg, Md. He believes that new types of targets can do the job just as well, and at a lower cost.

If Silver's belief proves true, that would certainly be good news for chip manufacturers facing the difficulty and cost of moving to expensive new hardware to produce overlay measurements. "The day is drawing near, within the next few miniaturization rounds, when chip manufacturers will have to begin adopting alternate measurement techniques," he says.

Chip fabrication requires instruments to measure the distances between a target on one chip layer and the matching lines on a target located on the layer directly above. The measurements are used to calculate the offset dimensions between the levels. Since a state-of-the-art microprocessor chip might have as many as 28 levels, determining the relative position of any two targets must be achieved with a precision of only a nanometer or two.

Chip feature dimensions are already dwarfed by the wavelength of visible light, making it increasingly difficult to use standard optical measurement techniques to measure relative positions. As chipmakers strive to maintain precision levels on ever-denser chips, Silver notes they will eventually have to turn to alternate technologies, most notably atomic force microscopes, to make the necessary measurements.

But atomic force microscopes are far from an ideal solution, Silver says. "The technology is slower and more expensive than the rapid, non-destructive optical techniques already used for overlay measurements," he states. "The industry could really use a better approach." Silver's alternative method would have chipmakers switch to improved target designs to check the precision and accuracy of overlay measurement equipment, and thereby ensure the precision of overlay measurements.

Silver and his colleagues have modeled target patterns that resemble slightly overlapping nanoscale picket fences. Together, the two sets of densely arranged nanoscale lines and grooves create a hybrid target that strongly reflects light, creating an image measurable with a conventional optical microscope. The individual line sets are so dense that no individual optical image of the lines appears, yet the combined superstructure results in the new unique optical pattern. "Because of the superstructure, we call it a 'super target,' Silver says.

Silver notes that the intensity patterns of the reflected light are unique to the combination, and the patterns are easily analyzed to determine the relative position of the lines that comprise the pattern. In the modeling studies, feature sizes ranging from 10 nm to 50 nm were positioned as close as 100 nm apart, beyond the theorized limits of resolution. The combined pattern greatly magnifies, by better than 40 times, the size of the overlay offset between layers.

"Being able to design optical targets, engineer the illumination, and then continue to use optical techniques is something that we can already start to apply within industry metrology tools," Silver says. He notes that his research has generated significant interest from the semiconductor industry and that NIST is now working with several partners to fabricate prototype targets with the new geometry.

"The beauty of this technique is that it can have an impact within a year or two," Silver says. "It doesn't require a substantial redesign of the current optical systems."


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