Breaking News: RASER High-Speed Serial Interface

Sept. 1, 2003

Taking aim at the popular PCI Express serial interface, designers at Rambus Inc. optimized a version of the company's RASER high-speed serial interface to fully comply with PCI Express specifications. Samples of a four-lane PCI Express physical-layer (PHY) interface chip are available immediately. The cells used to implement the chip can also be licensed from Rambus for use in FPGAs, ASICs, and other system solutions.

Implemented on a 0.13-µm process from TSMC, Rambus' manufacturing partner, the PCI Express PHY chip can be cascaded so systems can implement PCI Express interfaces with four, eight, 16, or 32 lanes. Additionally, the PHY cells consume just 80 mW per lane. The cell is based on a proven serializer/deserializer cell used in InfiniBand and Ethernet XAUI interfaces.

The company also offers a configurable physical coding sublayer that provides a flexible interface to the PCI Express media access controller and upper logic layers. Initial licensees of the RASER PHY include ALi Corp., which plans to use the cells in its mainstream core logic chip set for PCs, and eSilicon Corp., which will offer ASICs with the high-speed serial interfaces.

For more, go to www.rambus.com, www.ali.com.tw, and www.esilicon.com.

About the Author

Dave Bursky

Technologist

Dave Bursky, the founder of New Ideas in Communications, a publication website featuring the blog column Chipnastics – the Art and Science of Chip Design. He is also president of PRN Engineering, a technical writing and market consulting company. Prior to these organizations, he spent about a dozen years as a contributing editor to Chip Design magazine. Concurrent with Chip Design, he was also the technical editorial manager at Maxim Integrated Products, and prior to Maxim, Dave spent over 35 years working as an engineer for the U.S. Army Electronics Command and an editor with Electronic Design Magazine.