PCI Express Chip Packs 8/16-Bit PIPE Host System Port

Aug. 18, 2005

The GL9711 GigaCourier from Genesys Logic provides a 125-MHz 16-bit or 250-MHz 8-bit PIPE (PHY interface for PCI Express) interface to tie into the host system logic. This chip also offers a single-lane, 2.5-Gbit/s PCI Express serial port. With its parallel interface, system designers can add a PCI Express port to their systems without requiring a high-speed FPGA or ASIC.

The company plans to release a four-lane transceiver version of the chip, the GL9714, which it expects to sample next quarter. Both versions fully comply with the PCI Express base specification (revision 1.0a) and the PIPE architecture, version 1.0 from Intel Corp. Multiple four-lane transceivers can be used in systems that require 8, 16, or 32 lanes to meet the data-transfer needs of graphics, storage, and other applications.

In 25,000-unit quantities, the single-lane GL9711 sells for about $5 each. Samples are immediately available.

Genesys Logic America Inc.www.genesyslogic.com

About the Author

Dave Bursky | Technologist

Dave Bursky, the founder of New Ideas in Communications, a publication website featuring the blog column Chipnastics – the Art and Science of Chip Design. He is also president of PRN Engineering, a technical writing and market consulting company. Prior to these organizations, he spent about a dozen years as a contributing editor to Chip Design magazine. Concurrent with Chip Design, he was also the technical editorial manager at Maxim Integrated Products, and prior to Maxim, Dave spent over 35 years working as an engineer for the U.S. Army Electronics Command and an editor with Electronic Design Magazine.