65-nm Processes Target Next-Gen High-Speed And Low-Power ASICs

July 7, 2005
A pair of 65-nm CMOS processes lets designers implement ASICs with up to 120 million gates. Developed by IBM, these processes deliver twice the number of gates of the company's previous 90-nm offerings. These copper- and low-k-based processes als

A pair of 65-nm CMOS processes lets designers implement ASICs with up to 120 million gates. Developed by IBM, these processes deliver twice the number of gates of the company's previous 90-nm offerings. These copper- and low-k-based processes also can achieve a gate density of 615 kgates/mm2 while keeping the power dissipation to less than 5 nW/MHz/gate.

One process fits low-power designs, while the other suits high-performance applications. Both can set up voltage islands to control power consumption and use multiple-threshold-voltage library building blocks to balance performance and power requirements. They also incorporate strained-silicon structures that can improve the transistor performance by as much as 40% over non-strained devices (see the figure).

Design support for both processes includes tools that provide integrated noise, power, and timing methodologies to enable first-pass success. The tools use statistical techniques in timing and optimization to address process variations. This lets designers correct errors that might previously have gone undetected and re-engineer the chip throughout the design flow, achieving a more robust design.

Standard-cell design libraries, multiple I/O families, embedded SRAM and DRAM, embedded processors, and a wide range of packaging options support the processes. A broad selection of additional intellectual property (IP), including high-speed serializer-deserializers (SERDES), also supports the processes.

The low-power process (Cu-65LP) can trim leakage currents by as much as 30 times more than IBM's previous 90-nm ASIC. Transistor leakage is as little as 0.01 nA/µm when the chips are powered by a 1.2-V supply.

The per-gate power dissipation of 5 nW/MHz is just slightly lower than the active power of the 90-nm process. Yet the overall average power for an ASIC implemented in the Cu-65LP process is significantly lower thanks to the reduced leakage current. A design kit for the low-power process is now available, but volume production of chips designed for the process won't be ready until the first quarter of 2007.

Pushing the high-performance limits, the Cu-65HP process targets high-frequency performance-driven applications in networking, communications, data processing, and storage networks. It can deliver about a 20% performance increase over IBM's 90-nm process while operating from a 1-V supply.

Gate delays ranging from 6 to 9 ps are possible, while power dissipation is just 4.5 nW/MHz/gate. The design kit will be available in the fourth quarter of this year, with volume production of Cu-65HP devices projected for the third quarter of 2007.

Contact the company for development and production costs.

IBM Corp.www.ibm.com/chips
About the Author

Dave Bursky | Technologist

Dave Bursky, the founder of New Ideas in Communications, a publication website featuring the blog column Chipnastics – the Art and Science of Chip Design. He is also president of PRN Engineering, a technical writing and market consulting company. Prior to these organizations, he spent about a dozen years as a contributing editor to Chip Design magazine. Concurrent with Chip Design, he was also the technical editorial manager at Maxim Integrated Products, and prior to Maxim, Dave spent over 35 years working as an engineer for the U.S. Army Electronics Command and an editor with Electronic Design Magazine.

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