Platform ASICs—Designing Systems With Platform ASICsSponsored by: LSI LOGIC CORP.

March 15, 2004
Crafting system solutions with platform ASICs can be as simple as 1, 2, 3, once you understand how ASICs, platform/structured ASICs, and FPGAs differ.

Until recently, designing a complex system-on-chip (SoC) solution often meant taking 18 to 24 months to craft a full application-specific IC from the ground up, using standard cell libraries, blocks of intellectual property (IP), and custom-designed logic functions. But today, the cost to design the chip and fabricate it is escalating as the process feature size decreases from 180 to 130 nm and from 130 to 90 nm. Additional design options are needed to keep costs at tolerable levels. The higher costs and design complexity may end up limiting the number of designs that will use the full ASIC design approach.

Large FPGAs sit at the other end of the design spectrum. Although they offer lower design overheads and short implementation times, their limited and fixed on-chip resources and con-strained gate counts often limit the application complexity and performance levels that designs can achieve. FPGAs are also less area-efficient than ASICs because most FPGA approaches use logic cells that include blocks of static RAM or flash-memory cells to hold the configuration data. FPGAs, however, meet many of the system design needs for much less complicated designs. Many applications can use FPGAs to meet cost and time constraints.

Thus, a significant design gap lies between the ASIC and FPGA approaches. The industry has started to fill it with an intermediate solution that combines much of the performance and flexibility of ASICs with a portion of the time-to-market advantages of FPGAs. Known as "platform" and "structured" ASICs, these chips contain pre-designed functions ranging from memory blocks, high-speed I/Os, phase-locked/delay-locked loops, and still more complex functions. Along with the predefined functions is typically a large fabric of uncommitted logic gates or higher-level logic building blocks in which the system designer can configure the custom logic that uniquely defines the system functionality. This uncommitted logic area, as well as the rest of the chip, can be configured with one to five levels of metal or via interconnect, depending on the vendor’s offering.

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About the Author

Dave Bursky | Technologist

Dave Bursky, the founder of New Ideas in Communications, a publication website featuring the blog column Chipnastics – the Art and Science of Chip Design. He is also president of PRN Engineering, a technical writing and market consulting company. Prior to these organizations, he spent about a dozen years as a contributing editor to Chip Design magazine. Concurrent with Chip Design, he was also the technical editorial manager at Maxim Integrated Products, and prior to Maxim, Dave spent over 35 years working as an engineer for the U.S. Army Electronics Command and an editor with Electronic Design Magazine.

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