DDR Memory-Interface Core Eases DRAM Controller Design

June 7, 2004
Although known for its proprietary and high-performance memory interfaces, most notably the RDRAM and more recently the XDR, Rambus Corp. has decided to go mainstream. The company has used its high-speed design expertise to create a memory-interface...

Although known for its proprietary and high-performance memory interfaces, most notably the RDRAM and more recently the XDR, Rambus Corp. has decided to go mainstream. The company has used its high-speed design expertise to create a memory-interface block of intellectual property that can be used by DDR1, DDR2, and the three generations of graphics double-data-rate (DDR) memories (GDDR1, 2, and 3).

The DDR interface cell offers a complete solution that can tie the control logic to the specific DDR memory option. The company also will offer its design expertise to help companies create custom system solutions.

For most consumer and graphics applications, the interface core comes in two versions. The first is a "mainstream option" that ties into GDDR1 (400 MHz to 1 GHz) DRAMs and DDR2 (400-800 MHz) DRAMs. It also can offer an optional XDR interface mode. The second is a "performance" option that ups the GDDR speed to 1.6 GHz but is otherwise the same as the mainstream version.

For main memory applications, two versions of the core are available. The mainstream version handles DDR1 (200-400 MHz) or DDR2 (400-667 MHz) memories. The performance version handles DDR2 (400-800 MHz) memories and offers an optional XDR mode.

The need for DDR memory interfaces is growing. Many system products, from consumer systems like DVD players and games to desktop and industrial computers, now use DDR memories. Rambus' interface cell can be scaled to provide a data bus or address bus in any width. Most other memory interface offerings take a more "do-it-yourself" approach, offering single-pad I/O cells and a delay-locked-loop/phase-locked-loop block. Users must then concatenate the blocks to create the desired solution.

The first implementations that will be offered include the mainstream GDDR1 cell, which has been qualified on TSMC's 130 nm "G" process, and the performance version, which is qualified on TSMC's 90-nm GT process.

Rambus Corp.www.rambus.com
About the Author

Dave Bursky | Technologist

Dave Bursky, the founder of New Ideas in Communications, a publication website featuring the blog column Chipnastics – the Art and Science of Chip Design. He is also president of PRN Engineering, a technical writing and market consulting company. Prior to these organizations, he spent about a dozen years as a contributing editor to Chip Design magazine. Concurrent with Chip Design, he was also the technical editorial manager at Maxim Integrated Products, and prior to Maxim, Dave spent over 35 years working as an engineer for the U.S. Army Electronics Command and an editor with Electronic Design Magazine.

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