High-density NAND flash memories are key components in the burgeoning consumer market. Applications are rapidly expanding
beyond USB keys and MP3 players to cell phones, media players, and
game stations. This market is characterized by an ever-increasing
demand for greater memory capacities and lower cost per bit.
Multilevel-cell (MLC) technology, where each NAND flash memory cell
stores two or more bits of data, offers significant benefits in density and
cost. Yet its data retention and memory cycling performance pale next to
single-level cell (SLC) NAND flash memories. That's why MLC NAND flash
memories require error-correction-code (ECC) schemes that are much
more complex to meet product requirements for data integrity.
The cell architectures for SLC and MLC NAND are very different and
require substantially different ECC solutions. ECC has been used in many
applications for decades and has an excellent track record in military,
aerospace, and server applications. In typical flash applications, hardware detect and software correct is the most widely used solution.
Hamming, Reed Solomon (RS), and Binary BCH codes are the most
common algorithms used for ECC. They represent a large class of random error-correcting codes and sub-classes. Hamming and RS are mostly used for flash memory devices. The Hamming or shortened Hamming
codes are mostly used for single bit correction.
RS usually is better for multisymbol applications where the errors are
connected or grouped. BCH is better suited for random errors that have
no relationship with each other. Also, BCH is one of the better solutions
for current and future SLC and MLC device types.
