Based on the third-generation, 2.5-ns SuperFAST architecture, the ispMACH 4000V family of CPLDs now includes members that operate from 3.3-V supplies. The line's 32-, 64-, 128-, 256-, 384- and 512-macrocell versions can be had with operating voltages of 1.8, 2.5, or 3.3 V. The CPLDs offer maximum clock speeds of up to 380 MHz and a 2.5-ns tPD (pin-to-pin logic delay). I/O counts range from 30 to 208 across the family.
At 32 macrocells, the ispMACH 4032 provides a 2.5-ns tPD, a 2.2-ns clock-to-output delay (tCO), a 1.8-ns set-up time (tS), and a 380-MHz operating frequency. These numbers are about 25% faster than other available competitive devices. At the high end, the ispMACH 4512 packs 512 macrocells and, provides a 3.5-ns tPD, a 3-ns tCO, a 2.2-ns tS, and a 300-MHz maximum clock. These numbers make the chip about 58% faster than available competitive devices.
The ispMACH 4000V models have a static current as low as 1.3 mA. Coupled to the lowest voltage option of 1.8 V, they offer the industry's lowest dynamic power consumption—typically 78% less power at 100 MHz than other available 2.5-V CPLDs. The chips support LVTTL and multiple LVCMOS interface standards. The I/O cells are set up in two independent banks, each with its own power-supply voltage that can be set to support the desired standard. All of the ispMACH 4000 devices are boundary-scan testable (IEEE 1149.1) and in-system programmable through an IEEE 1532-compliant JTAG boundary scan interface.
In high volumes, prices start at less than $1.00 for the ispMACH 4032C, while the ispMACH 4512C will sell for less than $15.00.
Lattice Semiconductor
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