Reaching new memory-interface performance levels for graphics memories, the GDDR (graphics double-data-rate) III memory controller can handle data rates of up to 1.6 Gbits/s per I/O pin. Developed by TriCN, it employs the JEDEC standard stub-series-terminated logic-18 (SSTL-18) I/O levels. It's backward-compatible to the DDR II interface technology.
Available as a block of intellectual property (IP), the interface is implemented in TSMC's 90-nm process. Also available is another block of IP, a multifunction I/O (MFI/O) memory interface core. This block will recognize and self-configure to operate in one of a variety of standard interface modes, providing the flexibility found in FPGAs for ASIC applications.
The core can configure itself to SSTL-2, SSTL-18, HSTL-18, and HSTL-15 interface levels. It supports DDR-SDRAMs, DDR II SDRAMs, DDR and QDR SRAMs, and RL-DRAMI II interfaces. For the HSTL-15 interface, the core operates at up to 300 MHz, while it will run at 333 MHz for the other three options. This core is available for use on TSMC's 130-nm process.
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