Though the DS25C400 quad serializer/deserializer (SERDES) chip leverages backplanes intended for top data rates of 622 Mbits/s, it can deliver data at rates of 2.125 to 2.5 Gbits/s. All the while, transmit jitter levels are kept to just 0.25 UI and receive differential jitter is kept to 0.5 UI with no equalization and less than 0.75 UI with equalization.
The transmit section of each of the four serial channels includes a low-jitter clock synthesizer, an 8- or 10-bit parallel-to-serial converter with built-in 8b/10b encoder, and a current-mode logic output driver with selectable preemphasis. Each receive section contains an input-limiting amplifier with on-chip termination and selectable equalization levels, a clock/data recovery phase-locked loop, a comma detector, and a serial-to-parallel converter with built-in 8b/10b decoder. Built-in self-test logic lets the chip perform local loopback tests to verify operation.
Due to the SERDES' robust operation, the chip can be used on FR4-based backplanes typically designed to handle 622-Mbit/s low-voltage differential signaling (LVDS) signals. Designers can replace the LVDS circuits with DS25C400s and increase the data rate by a factor of four. Systems like routers, switches, cross connects, and multiplexers can then get performance upgrades without significant redesign. The on-chip preemphasis circuitry helps compensate for intersymbol interference, even when driving cables up to 10 to 20 meters. Also, the configurable equalization lets the receive portion reliably recover data.
The DS25C400 operates over the full -40°C to 85°C industrial temperature range. It consumes less than 2 W, typical, with all channels driving and receiving data at 2.5 Gbits/s. A thermally enhanced 324-ball PBGA package minimizes thermal management and airflow issues. The parallel-bus host interface can tie into 1.8-V SSTL, HSTL, or CMOS logic levels. All interface signals include hot-plug protection and termination resistors.
Samples of the DS25C400 are immediately available. Volume production will start in the first quarter of 2003. In lots of 1000, the chip costs $58.45 each.
National Semiconductor, (408) 721-5000; www.nsc.com.
About the Author
Dave Bursky
Technologist
Dave Bursky, the founder of New Ideas in Communications, a publication website featuring the blog column Chipnastics – the Art and Science of Chip Design. He is also president of PRN Engineering, a technical writing and market consulting company. Prior to these organizations, he spent about a dozen years as a contributing editor to Chip Design magazine. Concurrent with Chip Design, he was also the technical editorial manager at Maxim Integrated Products, and prior to Maxim, Dave spent over 35 years working as an engineer for the U.S. Army Electronics Command and an editor with Electronic Design Magazine.