Will Moore's Law Run Into A Power Roadblock?

March 2, 2006
Welcome to One Powerful Issue, with a special focus on power—the unifying force in the designs you're working on, from the most compact in-ear Bluetooth headset to the fastest Global Hawk UAV. Power-integrity issues often are the most

Welcome to One Powerful Issue, with a special focus on power—the unifying force in the designs you're working on, from the most compact in-ear Bluetooth headset to the fastest Global Hawk UAV.

Power-integrity issues often are the most daunting challenge in staying on the roadmap for semiconductor scaling, the exponential downsizing anchored by Moore's Law. Indeed, the growing impact of power on system-on-a-chip design was one of the hot topics at last month's DesignCon conference Santa Clara.

During the conference, I stopped in at Intel's lobby museum. It featured a 3D version of the original article where Gordon Moore had voiced the vision that became his eponymous law. "Cramming more components onto integrated circuits" was published in Electronics magazine in April 1965. (By the way, Electronic Design acquired Electronics in 1988. So, we'll claim a connection to Moore's famous look ahead—arguably the most consequential trade magazine article ever published.) With power-integrity issues fresh in my mind from the conference, I thought to take a look at what Moore originally had said about power density and heat.

Moore wondered about the possibilities for removing the heat generated by tens of thousands of components on a single chip. But he felt that "as long as a function is confined to a small area on a wafer, the amount of capacitance which must be driven is distinctly limited." Today, designers are working to pack and stack so much function into every area of the chip, it's understandable why Moore's vision runs into power blockades.

Still, Moore's article was remarkably prescient. In the next section of his article, "Day of reckoning," he goes on to say that "it may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected." This "disintegration," of course, is one of the solutions that Intel and other companies are pursuing as we move into the era of dual-core and multiprocessor designs that help solve heat and power-generation problems.

Even as we figure out ways to keep Moore's Law on track via smaller geometries, new power-design challenges rise to the fore. "This is the age of the client," said DesignCon keynoter Brian Halla, CEO of National Semiconductor. He was describing today's market, which is driven by mobility and content access.

"I've never seen a more optimal time for technology," said Halla. He also asserted that another dot-com boom is happening now. The previous decade, he said, offered an " infrastructure" boom—the equivalent to the railroad era's laying of the track.

In the first boom, he said, only 2.7% of the installed fiber was lit. Now, the pipes are being filled with the explosion of digital content including music and video, as well as the coming wave of machine-to machine communications. Plus, people want access to personalized content via devices that can connect wirelessly wherever they are.

Out on the DesignCon exhibit floor, the infrastructure build-out also seemed to be gearing for another growth wave, at least in terms of a speed overhaul. The drive for ever-faster communications was evidenced by the number of companies showing the tools to go beyond 10G Ethernet and on to the 25G range.

These tools require new designs not only for communications processors but also for every system component. Such technologies range from high-speed test equipment like the BertScopes shown by SyntheSys Research, through new cable assemblies from W.L. Gore, to card-edge connectors from FCI or Amphenol's Crossbow Matrix midplane connectors, all enabling data rates up to 25 Gbits/s.

I had dinner with some of the officers of the new Ethernet Alliance, a group working to define the next generation of Ethernet (target speed between 80 and 120 Gbits/s). The group is the clearinghouse for Ethernet design issues, including power over Ethernet and power over optical. The alliance aims to provide a problem-solving resource for designers implementing both core and network solutions.

The future of electronics is exciting. But it's going to take your continued innovations in power design and power management to keep design moving ahead at its current astounding rate of change. We hope this issue will inspire some new ideas. To read the original Moore article or for links to companies referenced in this column, go to www.electronicdesign.com and enter Drill Deeper 12087.

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