Breaking News: Second-Generation Reduced-Latency DRAM

Nov. 10, 2003

First samples of the second-generation Reduced-Latency DRAM are being released by Micron Technology Inc. These 288-Mbit devices operate at 400 MHz and use double-data-rate signaling for data transfers. The RLDRAM II chips also offer fast random access with extremely high bandwidth and high density. The memories can achieve a peak bandwidth of 28.8 Gbits/s using a 36-bit interface and a 400-MHz system clock. The chips have a low latency and a random cycle time (t_RC) of 20 ns, providing optimum bus-utilization efficiencies. Also included are on-die termination, multiplexed or nonmultiplexed addressing, on-chip delay-locked loop, common or separate I/O, programmable output impedance, and a 1.8-V core. The RLDRAM II chips come in 11- by 18.5-mm, 144-ball FBGA packages. See www.micron.com for details.

About the Author

Dave Bursky | Technologist

Dave Bursky, the founder of New Ideas in Communications, a publication website featuring the blog column Chipnastics – the Art and Science of Chip Design. He is also president of PRN Engineering, a technical writing and market consulting company. Prior to these organizations, he spent about a dozen years as a contributing editor to Chip Design magazine. Concurrent with Chip Design, he was also the technical editorial manager at Maxim Integrated Products, and prior to Maxim, Dave spent over 35 years working as an engineer for the U.S. Army Electronics Command and an editor with Electronic Design Magazine.