Doubling the storage capacity of a NAND flash memory using multilevel charge (MLC) storage lacks the high data integrity that data and program storage applications need. The X2 storage scheme, developed by M-Systems of Fremont, Calif., and Tokyo's Toshiba Corp., breaks new ground by enabling the use of double-density NAND-based storage technology for such applications.
To accomplish that feat, X2 adds special on-chip circuitry and custom software algorithms to the MLC NAND memory to boost reliability and performance levels to rival those of single-bit-per-cell storage schemes. As a result, the MLC NAND storage devices can hold local data and program code for cell phones, PDAs, and other systems that can't tolerate bad bits.
The circuitry and algorithms added to enhance the MLC NAND devices overcome the data-reliability, performance, and flash-management issues that held the MLC NAND back from use in local data and code-storage applications (see the figure). The X2 technology integrates seamlessly into M-Systems' DiskOnChip architecture and is fully compatible with the company's True Flash File System (TrueFFS).
To ensure that data remains valid, X2's enhanced error-detection and error-correction schemes consist of on-chip circuitry that detects errors on-the-fly. Its embedded software helps correct detected errors. The combined hardware and software can find and fix up to two errors per page without performance penalties. Hamming coding and BCH (Bose, Chaudhuri, and Hocquenghem) coding provide extra robustness, permitting the algorithms to correct up to four errors per page.
To overcome access and partial programming limitations, X2 includes the customized Sequential Access Flash Translation Layer (SAFTL). This layer maps each virtual unit into a chain of physical units, much like the way translation layers work for single-bit-per-cell flash memories. Yet unlike traditional translation layers, SAFTL doesn't implement one-to-one simple mapping between the virtual sector offset in the virtual unit and its physical location in the physical units. Rather, the data of a virtual sector can be in any location within the physical unit chain of its virtual unit.
Thus, each physical unit can be filled sequentially, starting from the first sector to the last. Each write request to the corresponding virtual unit is written to the next free physical sector, regardless of the virtual sector number requested to be written. When a physical unit is full and a new write request arrives, a new free physical unit is allocated and added to the chain. New unit allocation always occurs concurrently with writing a sector. As a result, the sector data and the unit control data can be written in one operation to improve performance.
X2 handles bad blocks, which can be randomly present in flash media, by enabling unaligned block access to two memory planes. Without this capability, a bad block in one plane would cause a good block in the second plane to be tagged as a bad block, making it unusable.
To improve read performance, the X2 scheme calls on its MultiBurst feature. This enables parallel read access from two 16-bit planes to the flash controller, achieving the desired output data rate for the host. The host accesses the first word of a page with a relatively slow access time, but each subsequent word is accessed more quickly.
X2 reduces CPU overhead by including direct memory access (DMA) capability. This is beneficial when transferring large files in support of real-time operating systems. Overall system performance can be stepped up by reducing boot time. In this case, large blocks of code get transferred from the NAND flash array into shadow RAM.
M-Systems plans to incorporate the X2 technology into its DiskOnChip, DiskOnKey, and fast flash disk family product lines. These families will offer devices with twice the storage capacity for about the same price as existing family members, as well as lower-cost versions with capacities equal to those of existing family members.
Contact M-Systems at www.m-sys.com for more details.