Select The Optimum ASIC ApproachSponsored by: FREESCALE SEMICONDUCTOR

Nov. 15, 2004

Requirements of high speed for data networs and high frequency for broadband systems make the selection of the best ASIC approach critical for both performance and cost.

Dave Bursky

When pushing the performance of a custom network processor or widening the bandwidth of a next-generation broadband interface, the performance of the customized chips used in the system banks heavily upon selecting the best implementation approach. CMOS FPGAs, structured/platform ASICs, and full custom ASICs provide a broad array of design options for all digital systems. Within the custom ASIC arena, designers now have the choice of a "standard" CMOS process, or for performance/power-critical designs, silicon-on-insulator (SOI) CMOS processes. New options also are appearing for designs at the leading edge. For example, strained silicon enhances electron mobility in the gate region, improving transistor switching speed.

For the mixed-signal portion of the design, the choice of approaches is often limited to either a cell-based or full-custom approach because few off-the-shelf "platforms" include analog or mixed-signal functions, save for phase-locked loops or a few specialized I/O cells. But while the choice of approaches is smaller, the actual implementation scheme choice becomes more complicated. Technologies such as biCMOS, silicon germanium (SiGe), SOI, and shallow trench isolation can help push performance to the limit when standard CMOS won't fit the bill. Table 1 lists several technology options and provides some perspective on which technologies are best applied to different technical requirements.

Pick The Best Recipe Bulk CMOS processes are the most common, and they're available from many ASIC suppliers. The processes are typically available in a wide range of feature sizes, from legacy 0.35-µm low-cost/low-performance processes with a few levels of aluminum interconnect to the latest 0.09-µm high-performance processes with nine or more layers of copper interconnect. Such processes support a wide range of applications, from very cost-sensitive products such as cell phones to high-performance processor-based products for networking and computing systems.

By placing a thin, insulating layer such as silicon dioxide between the active layer of silicon and the silicon (or other material) substrate, circuits can operate faster and/or consume less power because the insulating layer reduces parasitic capacitances that often cause performance losses as operating speeds go up. SOI can be a cost-effective option if power consumption or absolute, top-notch performance is a critical concern.

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About the Author

Dave Bursky | Technologist

Dave Bursky, the founder of New Ideas in Communications, a publication website featuring the blog column Chipnastics – the Art and Science of Chip Design. He is also president of PRN Engineering, a technical writing and market consulting company. Prior to these organizations, he spent about a dozen years as a contributing editor to Chip Design magazine. Concurrent with Chip Design, he was also the technical editorial manager at Maxim Integrated Products, and prior to Maxim, Dave spent over 35 years working as an engineer for the U.S. Army Electronics Command and an editor with Electronic Design Magazine.