CMOS Logic Family Delivers Shortest I/O Delays, Wide Interface Options

Offering a wide selection of devices with interfaces compatible with AVC, LVCMOS, ALVC, and ALVCH is International Microcircuit's latest quartet of logic families. Featuring transceivers, buffers, drivers, and PLL-based clock generators, the circuits also include a variable-output impedance capability that helps eliminate noise. This, in turn, improves the performance of servers, workstations, routers, and other high-speed systems.

Incorporated within this series are advanced very low-voltage CMOS (AVC) series devices that can increase bus performance by 40%. This is achieved through a combination of short propagation delays (just 1.2 ns), a variable-output impedance control, a low output skew, and very low intrinsic jitter. Such performance characteristics will allow engineers to increase their timing budget. Consequently, they can attain the maximum possible bus performance in their systems.

The variable-output impedance control automatically changes the impedance of the output drivers during signal transitions to minimize undershoot and overshoot. Another benefit of these devices is that they maintain a carefully controlled slew rate of 1- to 2-V/ns to reduce noise. With its low-voltage swings and high operating frequency, AVC technology promises to be one of the future standards for support logic. Transceivers, buffers, drivers, registers, and very high-performance PLL-based clock generators (PLLs offered in LVCMOS) also complement this series.

In addition to AVC technology, most of the functions are available in low-voltage CMOS (LVCMOS), advanced low-voltage CMOS (ALVC), and advanced low-voltage CMOS with bus hold (ALVCH). The devices will be implemented in the design of new high-speed buses. They also will be used in existing memory subsystems that employ standards such as PC100 (100 MHz), PC133 (133 MHz), PC166 (166 MHz), and DDR (266 MHz). Furthermore, these logic family members can be used in add-in cards, dual-in-line memory modules (DIMMs), and other external modules.

To handle parity and other detection schemes, the buffer and transceiver devices are available in bus widths of 16 and 18 bits. The outputs of the devices can drive an impedance of 50 Ω with a capacitance of 50 pF. Within the new product line are phase-locked-loop (PLL) clock chips. These chips integrate the buffers and transceivers to regenerate the clock signal, thereby reducing skew and jitter. The clock devices have a skew of less than 150 ps (between output clocks) and a cycle-to-cycle jitter of less than 100 ps peak.

All devices are available in sample quantities. They will be offered in a variety of packages, including TSSOP, SSOP, and TVSOP. Prices range from about $1.02 apiece for the basic ALVC buffers and transceivers to $6.75 each for the DDR registers and PLL circuits, all in quantities of 1000.

International Microcircuits Inc., 525 Los Coches St., Milpitas, CA 95035; Mark Sherwood, (408) 263-6300; Internet: www.imicorp.com.