Get A 40% Boost In Speed And Utilization Via Enhanced Tools

Sept. 20, 2004
Development tools for D-Fabrix, Elixent's reconfigurable algorithm processing (RAP) technology, have been upgraded. This means greatly enhanced performance for the D-Sign v1.4 tool suite, including a 4× drop in synthesis times and placement...

Development tools for D-Fabrix, Elixent's reconfigurable algorithm processing (RAP) technology, have been upgraded. This means greatly enhanced performance for the D-Sign v1.4 tool suite, including a 4× drop in synthesis times and placement speed. As a result, design productivity goes up while development time goes down.

The upgraded tools include full support for v1.2 of the D-Fabrix architecture and VHDL. The D-Fabrix architecture employs reconfigurable arrays of arithmetic elements. Algorithms can be mapped and changed post-fabrication on these arrays, allowing bugs to be fixed or the chip to be reused in a new application. Based on a new "place-and-route" technology, D-Sign v1.4 improves the mapping of an application onto the array. Gains in speed and utilization of up to 20% are achievable, boosting performance and density by more than 40%.

D-Sign v1.4 lets users automatically exploit the power-saving features of the v1.2 architecture--improved clock gating (which allows unused parts of the array to be turned off) and power-down/standby modes. The standby mode reduces power to just 1/1000 that of an FPGA. The VHDL support in D-Sign v1.4 now includes the full synthesizable subset of the IEEE1076-2002 definition of the language. This is in addition to the tool's existing comprehensive implementation of IEEE 1364.1 Verilog. Tool cost is part of a negotiated technology license agreement, but existing licensees can upgrade at no cost.

Elixentwww.elixent.com

Sponsored Recommendations

Comments

To join the conversation, and become an exclusive member of Electronic Design, create an account today!