In this generation of logic design, programmable logic is geared to become the favored platform for system-level integration (SLI). System-on-a-programmable-chip (SoPC) will then be the vehicle for system-on-a-chip (SoC) applications. These statements are provocative to the many engineers who don't think of programmable logic in that light. But the changing world is rapidly propelling us from the era of SoC into the era of SoPC.
Unlike ASICs, programmable-logic devices (PLDs) are manufactured as standard products. They benefit from the economies of scale in the manufacturing environment. Essentially, programmable logic puts the customer in control. During product development, for example, PLDs allow the engineer to devote precious time to design activities, like system integration and development of proprietary logic. This allows both product differentiation and faster time-to-market, the two critical success factors in the competitive marketplace. In production, programmable logic insulates the customer from the growing risks associated with a customized ASIC solution. These risks are driven by the ever-increasing cost of the modern wafer-fabrication facility.
Advancing technology is driving up the minimum order required to achieve economies of scale for an ASIC solution. At this point, only a select customer base can participate. Over the next few years, this phenomenon will result in a bifurcation of the market between ASICs and PLDs.
Traditional, cell-based ASICs will only serve high-volume applications. Of these, the highest-volume applications will go to ASSPs, especially in market segments where standards are already set. These chips will continue to be appropriate for the volume-driven, consumer-oriented products that require the lowest unit cost. The remainder of applications—driven by communications infrastructure products—will gravitate to the low risk, flexibility, and economies of scale offered by programmable logic. Over time, the ASSP of today will become the embedded IP in SoPC applications.
The move to PLD-based system integration is empowered by the devices' rising density. As a result, robust development tools are vital to the SoPC methodology. The need for tools to address high-level design is being boosted by specific forces. The first of these is new device capability, including multimillion-gate designs, higher performance, more effective utilization, and advanced features.
The computing environment has changed in recent years with the emergence of both multiprocessor systems and distributed computing. High-level design methodology demands productivity and efficiency enhancements, seamless integration with third-party EDA tools in the ASIC design flow, and new technology to break the verification bottleneck created by high-density designs.
Intellectual property (IP) is commonly associated with the ASIC platform. But Altera Corp. believes that PLDs are more closely aligned with the IP value proposition. The purpose of IP is to reduce development cost, speed time-to-market, and lower risk. These very qualities also make programmable logic attractive for high-density design.
Today, the industry stands at the doorway of the SoPC era. The proof is in the high-density devices, development tools, and enhanced embedded capabilities. Couple these with IP, and the result is system-level building blocks that can be user-parameterized. This combination—the total programmable solution—is why the platform of choice for system integration will be programmable logic.