Using standard 0.18-µm CMOS technology, Xilinx Inc. came up with a 10-Gbit/s implementation of the RocketPHY family of physical-layer (PHY) transceivers. In addition to offering standalone models, the company will also incorporate the PHYs into a just released Virtex II Pro X family of FPGAs.
The FPGAs and standalone CMOS 10-Gbit/s PHYs are the first CMOS implementations that will meet the Sonet jitter requirements. As a result, designers can implement a comprehensive solution for 10-Gbit/s Sonet systems.
The RocketPHY family has three members. The XGC1120 10G Ultra MSA supports Sonet OC-192, SDH STM-64, G.709, 10-Gbit Ethernet, and 10-Gbit Fibre Channel applications. The XGC1121-RocketPHY 10G Sonet/SDH supports Sonet OC-192 and SDH-STM-64 applications. The XGC1320-RocketPHY 10GbitE/FC supports 10-Gbit/s Ethernet and 10-Gbit Fibre Channel applications.
Samples of all three are available, with production scheduled for Q4. The chips come in 256-contact PBGA packages. In 2004, the XGC1120 will sell for $99, the XGC1121 for $89, and the XGC1320 for $79, all in 5000-unit lots. For details, see www.xilinx.com.
Also pushing data speeds to 10 Gbits/s is Aeluros' Puma, a XAUI to 10-Gbit serial interface chip. The chip has a bidirectional XAUI interface on the system side. Each direction consists of four 3.125-Gbit/s channels. The chip's network side includes a 10-Gbit/s low-jitter serial transceiver, but not low enough to meet the stringent Sonet jitter requirements. This chip consumes just 800 mW, which is about half the power consumed by most other 10-Gbit/s interface devices. Available in sample quantities, the Puma chip comes in a 13- by 13-mm package and costs $150. See www.aeluros.com for details.
