Write-Once Has A Place

July 7, 2003
The goal of most nonvolatile memory technologies is to retain data once it's written, but allow the data to be rewritten again and again. However, novel applications are opening opportunities for technologies that only allow data to be written once...

The goal of most nonvolatile memory technologies is to retain data once it's written, but allow the data to be rewritten again and again. However, novel applications are opening opportunities for technologies that only allow data to be written once and then retained, just like the old fuse-based, programmable read-only memories. If an extremely low-cost storage scheme can be implemented, it could open single-use applications in digital photography, digital music, and other applications where nonvolatile memory card costs were previously too prohibitive to justify one-time recording.

Designers at Matrix Semiconductor Inc., envisioning just such a market opportunity, crafted a one-time programmable memory technology based on antifuse and diode memory cells. One advantage of the technology is the ability to stack multiple layers of memory cells, one above the other, on top of the silicon so that no silicon area is consumed by the memory arrays. Only the control and sensing logic is integrated into the silicon, resulting in an extremely small chip. Another benefit is the polycrystalline material used for the storage array layers. It's extremely simple to deposit and doesn't require special process steps, which makes it extremely inexpensive.

Memory cells are formed at the intersection of bit lines and word lines, with each cell containing a P+ anode, an oxide antifuse, and an N- cathode. Prior to being programmed, the antifuse insulates the anode from the cathode and no current can flow in the diode (a logic "1"). Rupturing the antifuse (creating a short) joins the anode and cathode and allows current to flow (a logic "0").

The first proof of this technology was described earlier this year at the IEEE International Solid State Circuits Conference. In its paper, Matrix researchers discussed a 512-Mbit PROM that employs eight layers of antifuse/diode cells. A 3.3-V, NAND-style interface, with a read speed of 1 Mbyte/s and a write speed of 0.5 Mbytes/s, is used. A modified Hamming code performs error-checking and correction on the chip. For details, contact Matrix at www.matrixsemi.com.

About the Author

Dave Bursky | Technologist

Dave Bursky, the founder of New Ideas in Communications, a publication website featuring the blog column Chipnastics – the Art and Science of Chip Design. He is also president of PRN Engineering, a technical writing and market consulting company. Prior to these organizations, he spent about a dozen years as a contributing editor to Chip Design magazine. Concurrent with Chip Design, he was also the technical editorial manager at Maxim Integrated Products, and prior to Maxim, Dave spent over 35 years working as an engineer for the U.S. Army Electronics Command and an editor with Electronic Design Magazine.

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