Logic Line Slashes Mask And Silicon Costs

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Whether they're pressured to meet specifications and/or time-to-market, many industry members see IP platforms as their savior. Virage Logic is joining this fray with its first semiconductor IP platform. This family of Area, Speed and Power (ASAP) Logic products includes the High-Speed (HS) Metal Program-mable Cell Library and the High-Density (HD) Standard Cell Library.

Typically, the ASAP Logic products promise more than a 20% increase in logic-block-area utilization. The family's silicon has been proven on a variety of process geometries—0.25, 0.18, and 0.13 µm—at integrated device manufacturers. Now, the line is being introduced to fabless semiconductor customers on TSMC's 0.13-µm logic process.

Next to competitive standard cells, the underlying architecture provides the same performance with shorter cell sizes. With their patented routing and cell architecture, the ASAP Logic products are well suited for deep-submicron applications requiring optimized routability and minimized power consumption.

The ASAP HS Metal Programmable Cell Library promises to overcome high mask costs without causing performance degradation. Because of advances in pin accessibility and power routing, the HS Metal Programmable Cells provide area and performance that are similar to conventional standard cells. Yet they avoid the penalty of all-layer costs. If a revision is needed, the designer only has to redesign the block and a few metal and via masks.

The ASAP HD Standard Cell Library is tasked with reducing the overall cost of silicon. It leverages the ASAP Logic place-and-route and cell architecture for larger numbers of metal layers. That architecture also provides significantly increased pin accessibility, while eliminating cell placement blockage from the power grid.

For fabless customers, the ASAP HS Metal Programmable Cell Library licensing fee starts at $50,000 (U.S. list price) per design. The ASAP HD Standard Cell Library licensing fee starts at $25,000. Both products are available now on TSMC's 0.13-µm standard logic process.