Platform ASICs Deliver Cost-Effective SolutionsSponsored by: FUJITSU MICROELECTRONICS AMERICA INC.

Sept. 6, 2004
Some key points to consider for platform/structured ASICs
Shoehorn Anyone? When planning an SoC design using a structured or platform ASIC, the level of integration is an important consideration for optimum platform selection. The number of available gates and other on-chip resources indicate a platform's viability to contain your design. Examine the structured ASIC's logic architecture to determine the granularity of base logic cells and thus the flexibility you have when implementing your circuit. Also, when selecting a chip from a family, make sure you have room to grow so you can add features to the system later.Tic, Tic, Tic On-chip clock support and distribution are key resources when implementing high-performance designs. Such designs often use multiple clock domains, some of which can run from the same master clock, while some require independent clock sources. When examining the on-chip resources, evaluate the number and types of phase-locked loops, delay-locked loops, clock buffers, and predefined clock trees that are available. Also check the vendor's intellectual-property library and third-party support for additional timing support functions.Down Memory Lane Almost every SoC solution has on-chip static RAM to provide various storage resources—from simple registers to full data/instruction storage. Today's advanced processes allow from hundreds of kilobits to several megabits, with 3- to 10-ns access times, to be pre-integrated on the structured ASICs. Check out the hierarchy of the on-chip memory. Is it organized as a flat hierarchy with n-blocks of so many kilobits? Or, is it a hierarchy of small, medium, and large size blocks? When analyzing structured or platform ASICs, look for a variety of memory interfaces, such as Double Data Rate (DDR), Synchronous DRAM, RLDRAM or Fast Cycle RAM (FCRAM).

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