Quadrature Encoder-Decoder Is Implemented In A CPLD

Quadrature encoders have many uses in position-sensing applications. This implementation uses a Xilinx complex programmable logic device (CPLD) to count the pulses from the encoder and determine the direction indicated by those pulses (see the figure).

The design uses an up/down counter that reads Channel A. The counter is gated by the state of the B input. If B is high on the rising edge of the pulse received at input A, the counter counts up. If B is low, the counter counts down. This produces a 16-bit result that indicates the movement of the encoder shaft. The 16-bit data may be read by any 16-bit microprocessor data bus or port. A1 determines which counter is addressed. A write to either channel resets that channel to zero. The device was programmed in VHDL (available free from Xilinx). The idea may, of course, be implemented on any CPLD or FPGA. The VHDL source listing is available in the online version of this article at www.elecdesign.com.