System-On-A-Chip Design With Platform ASICs

Jan. 13, 2005

Where does the platform ASIC position itself versus other ASIC solutions?

A platform ASIC fills the design gap between the full cell-based ASIC design, which typically requires about 25 masks and a 12- to 18-month design cycle, and the in-system instantly configurable and off-the-shelf field-programmable gate array. Platform ASICs and their cousins, the structured ASICs, often can provide a lower-cost solution than a cell-based design when component volumes are a few hundred thousand units or less. As an alternative to the high-complexity FPGAs, the platform ASIC also can offer significant cost reductions once a design is "locked in" and unit volumes approach 5000 or more. Nonrecurring engineering charges are significantly lower than they are for cell-based designs as well, since only a few metal-mask layers must be customized versus the 25 or so layers a cell-based ASIC requires.

What differentiates a platform ASIC from other approaches?

A platform ASIC consists of a partially predesigned chip that contains a predetermined collection of resources, such as several hundred thousand to several million logic gates, several hundred thousand to several million bits of SRAM storage, phase-locked loops, high-speed serial I/O ports, general-purpose I/O pads, and embedded CPUs. The platform ASIC supplier may have multiple predefined platforms ready and waiting for customers. All the customer needs to do is supply a synthesized netlist, and the vendor's tools will convert the netlist into the metal wiring layers needed to finalize the chip. In contrast, cell-based ASICs are designed to order from the first diffusion layer to the final metal layer. And, FPGAs are fully fabricated chips that accept a stream of data bits that configure the RAM-based, flash-memory-based, or antifuse-based logic cells (see the table).

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