SOI Drops The Capacitor, Doubles Embedded DRAM Density

For over two decades, manufacturers of dynamic RAMs have used a simple one-transistor/one-capacitor structure for the basis of each storage cell. But an alternative to that design based on silicon-on-insulator (SOI) technology may double the density of DRAMs by eliminating the capacitor.

But if you eliminate the capacitor, where is the charge that represents the data bit stored? That's the magic of SOI. The active circuit layer is isolated from the substrate, so there's a capacitive "floating body effect" that can be used as an alternative to the discrete-trench or stacked-capacitor structures (see the figure).

Although this effect is widely known, the challenge has been to find a way to define charges to represent each bit and then to directly address and access the charges without disturbing the nearby charges that represent other bits. Innovative Silicon Inc. has developed such a solution for use in applications that need large amounts of embedded DRAM, like large level 3 caches and image storage.

The company's approach starts with a standard partially depleted SOI CMOS process. Yet designers expect that it can be scaled to fully depleted SOI CMOS, or double-gate and FinFET multigate transistor structures can be leveraged. The Z-RAM (short for zero-capacitance DRAM) requires no exotic materials and no extra mask steps to form the memory cells, simplifying the manufacturing flow.

In SOI structures, the floating body effect is usually an undesirable parasitic element. By controlling and then enhancing it with the transistor gain, though, Innovative was able to create a mechanism that can store "1" or "0" binary states.

An excess of positive or negative charges in an n- or p-channel device's body stores the data states. For an n-channel device, an excess of positive charges in the body decreases the threshold voltage. This increases the channel current, defining the state "1." An excess of negative charges in the body is obtained by removing the holes that are present. This decreases the channel current, defining the state "0." Data can be read by applying a small pulse to the selected bit-cell transistor and comparing the channel current to the current of a reference cell.

Implemented in a standard 90-nm SOI process, the memory cell can be as small as 0.1 µm². That's about one-tenth the size of the smallest SRAM cells and less than half the size of most DRAM cells. This bodes well for the economics of using an SOI process, which costs more than a bulk-CMOS process. But the smaller chip area possible with a large array of Z-RAM-based memory can reduce the cost per chip to levels competitive with bulk CMOS.

Megabit-size test arrays of memory cells have been fabricated at nine different foundries. The cells have demonstrated very short access times at power levels lower than most other embedded DRAM structures. The company expects to have the Z-RAM technology available for licensing during the second half of this year.