Get Up Close And Personal With Silicon Foundries

Aug. 18, 2005
To battle escalating chip design costs, designers forge deeper relationships with manufacturing partners to ensure "right first time" success.

IC designers and wafer foundries are becoming more intimate these days. Due to soaring design and manufacturing costs, the two camps find themselves working together earlier in the design cycle. This gives chip designers the wherewithal to craft top-performance circuits that are optimized for manufacturability and have a better chance of meeting specifications.

Electronic-design-automation (EDA) tool suppliers are forming closer relationships with foundries, too. Tool suppliers must work with the foundries to develop better manufacturing-related tools. At the same time, they also have to work with the chip-design companies to develop tools that shorten the design cycle and improve performance. On top of that, they must help customers further when verifying a design before the handoff to manufacturing.

The customers must perform lots of due diligence as well to ensure the foundry that they select has the EDA tool partners, libraries, and other partners that meet the project's needs. The sooner the dialogue starts between the customer and foundry, the better the chances for the design's success.

The three categories of companies—the customers, the foundries, and the tool suppliers—have aligned to form a virtual vertically integrated company to go from concept to product. In the years before foundries, large semiconductor companies were totally integrated. Some would go so far as to create their own wafers from molten silicon, write their own design tools, do the logic and physical design, create the masks, process the wafers, and then go on to the testing and packaging stages.

By having everything under one "roof," the teams could discuss optimizations and issues that affect performance and manufacturability. But the need to reduce overhead and the emergence of suppliers of standardized raw wafers, mask-making services, design tools, wafer-fabrication services (foundries), and so on ushered in changes to the "everything under one roof" approach.

Such changes let the large companies disaggregate. Traditional semiconductor vendors reduced their overheads by shedding portions of manufacturing flow and even EDA tool development, says Pankaj Mayor, the Group Director of Business Development at Cadence (Fig. 1).

"Once standardization entered the picture, the disaggregation caught on very quickly, with many companies looking to outside vendors to deliver generic services," says Mayor. "These vendors now form the beginning of what can be called the silicon design chain." This chain also can include the independent vendors of intellectual property as well as the test and packaging vendors.

DIVIDE AND CONQUER Disaggregation of the typical semiconductor supplier triggered the emergence of independent EDA tool vendors like Cadence, Mentor Graphics, and Synopsys. It also fostered the creation of independent wafer foundries, especially in the Far East.

For instance, there are Taiwan-based Taiwan Semiconductor Manufacturing Corp. (TSMC) and United Microelectronics Corp. (UMC). Chartered Semiconductor sets up shop in Singapore, while Silterra has its fabs in Malaysia. And, Semiconductor Manufacturing International Corp. (SMIC) is in China. Meanwhile, large semiconductor manufacturers like IBM and Freescale Semiconductor (formerly Motorola Semiconductor) have opened their doors to offer foundry services based on their well-established processes and IP libraries.

Designers now can outsource the manufacturing, design-tool creation, and test and packaging functions. A new "breed" of company, the fabless semiconductor vendor, has come to the fore as a viable alternative to the established vertically integrated company.

These companies can concentrate on what they do best—the definition and logic implementation of new circuits that will deliver outstanding performance. In the graphics world, companies such as ATI and nVidia are good examples of how well the process works. In the FPGA market, just about all of the vendors—Actel, Altera, Lattice Semiconductor, QuickLogic, and Xilinx—exemplify the successes achieved by foundry partnerships.

The disaggregated model has worked well for about two decades as feature sizes dropped from about 0.5 µm down to 0.35, 0.25, and 0.18 µm. But with smaller feature sizes of 130, 90, and 65 ns now pervading, more stringent processing requirements and design rules must be implemented. This will affect chip design and how those design teams must interact with foundries and tool vendors.

VOLUME, VOLUME, VOLUME Foun-dries are in business to sell large quantities of finished wafers. But to do that, their customer designs must be production-worthy. When manufactured, they must generate sufficient quantities (yield) that meet performance and cost targets. As a result, the logic design has to be correct. The physical layout also must be completed to maximize performance and yield while cutting power consumption, cost, and other criteria set by the designers.

To achieve this, foundries must work ahead of their customers. They also must work on more advanced issues such as variability, especially when tools aren't yet available. A three-way collaboration between the EDA/IP suppliers, the customer, and the foundry is needed to achieve a manufacturable design, explains Patrick Lin, chief system-on-a-chip (SoC) architect of System and Architecture Support Group at UMC.

Therefore, yield could become the new mantra recited by many as a host of design and manufacturing factors can affect yield. In manufacturing parlance, poor yield often means a lack of fully functional chips or chips that can't meet various performance criteria (clock speed, power consumption, and operating temperature range) due to parameter spreads in the manufacturing process.

A low yield would increase the cost per good chip to the customer, perhaps to an unacceptable level. If the chip is too expensive, it will go into limited production just to meet critical needs. Or, the project may be cancelled altogether. Of course, neither case is the foundry's desired scenario. The foundry wants to sell thousands of wafers per design, producing millions of the same chip per customer.

Today's advanced processes make the yield challenge harder than ever because many aspects of the physical design can affect yield (Fig. 2). All of the factors outlined in Figure 2 comprise part of another mantra that many companies are expounding—design for manufacturability (DFM).

BEWARE THE GOTCHAS The ability to achieve a manufacturable design has pushed foundries to work closer with the chip-designing companies. Foundries arm designers with the basic design rules plus a horde of guidelines that expand on these rules.

We can often refer to these extras as the "gotchas" in manufacturing. Through lots of analysis of failed designs and modeling of the physical characteristics, foundries such as Chartered, TSMC, and UMC have compiled many guides for the chip-design teams to ensure manufacturability.

Some advice imparted by those DFM guidelines include metal wire spacing to minimize the impact from random defects, the use of redundant vias to ensure layer-to-layer connections, and layout guidance to ensure the best transference of the pattern from the mask to the wafer surface. Optical proximity correction (OPC) is a good example of how the interface to the foundry is changing.

Foundries routinely use OPC to compensate for the way the features on the mask are transferred to the chip's surface. But by working with EDA tool vendors, the foundry can model the lithographic system—the equipment, resist, and etch—and then use that model in the OPC software to optimize the pattern transfer.

To deliver the best performance, several foundries now offer their own cell libraries in addition to the generic cell libraries they typically license from third-party vendors like Artisan and Virage Logic. For example, TSMC recently released two cell libraries—one optimized for high-performance and another for low-power operation.

According to Ed Wan, senior director of design service marketing, the tight library-technology coupling helps reduce design time and can help shorten the time-to-market. "Furthermore, the unique circuit-under-pad I/O cells allow designers to build functionality in the smallest possible chip area," says Wan.

Thanks to these internally developed libraries, designers can push the performance of their chips up a notch to achieve higher speed or lower power consumption, or some combination of the two. Because the libraries are "tuned" for the foundry's processes, though, they may limit the fabless company's ability to move the design to another foundry.

In addition to libraries, some foundries have added design services to help customers lacking in-house expertise to craft their chip. Silterra, for example, has developed its processes to match the processes offered by TSMC. In addition to the basic foundry services, Silterra provides design services through partner companies. Taking a different route, UMC actually spun out a company to offer ASIC and design support—Faraday Technology.

Independent design service companies such as Open Silicon offer an alternative to direct work with the foundry. Designers can hand off their RTL file, and Open Silicon will do the full implementation and work with the foundry to deliver finished chips.

A multicompany alliance between IBM, Cadence, Chartered Semiconductor, Magma Design Automation, and Synopsys provides the industry's first cross-foundry design enablement program to support leading-edge chip development starting at the 90-nm process node (Fig. 3). The collaboration bore fruit with a low-power reference flow for the 90-nm common process platform jointly developed by Chartered and IBM.

The Synopsys Galaxy design and Discovery verification platforms form the foundation of the reference design flow. They enhance the existing tool support by addressing power reduction, signal integrity, and DFM issues. The ARM/Artisan Metro low-power libraries were used for the flow development. And with Magma's RTL-to-GDS-II reference flow, designers can develop low-power SoC solutions while leveraging the flexibility of dual manufacturing sources (IBM and Chartered).


Cadence Design Systems Inc.

Chartered Semiconductor Manufacturing Ltd.

Faraday Technology Corp.

Freescale Semiconductor Inc.

IBM Corp.

Magma Design Automation Inc.

Mentor Graphics Corp.

Open-Silicon Research Private Ltd.

Semiconductor Manufacturing International Corp.

Silterra Malaysia Sdn. Bhd.

Synopsys Inc.

Taiwan Semiconductor Manufacturing Corp.

United Microelectronics Corp.

Virage Logic Corp.

About the Author

Dave Bursky | Technologist

Dave Bursky, the founder of New Ideas in Communications, a publication website featuring the blog column Chipnastics – the Art and Science of Chip Design. He is also president of PRN Engineering, a technical writing and market consulting company. Prior to these organizations, he spent about a dozen years as a contributing editor to Chip Design magazine. Concurrent with Chip Design, he was also the technical editorial manager at Maxim Integrated Products, and prior to Maxim, Dave spent over 35 years working as an engineer for the U.S. Army Electronics Command and an editor with Electronic Design Magazine.

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