Structured/Platform ASICs Carve A Cost-Savvy Niche

Nov. 7, 2005
Platform and structured solutions look to solve designer dilemmas caused by rising ASIC design costs.

Shrinking feature dimensions used in chipmanufacturing processes continue to push the complexity and density of the circuits to groundbreaking levels. But getting there comes with a heftier price tag when developing and fabricating high-end application-specific ICs (ASICs).

In fact, most research analysts agree that at the 90-nm process node, taking a cell-based ASIC from concept to production will run between $10 million and $15 million. Plus, when designs migrate to the 65-nm node, the overall development cost approaches $20 million.

Of course, for designs that don't push the edge on performance or complexity, processes that employ minimum features of 110, 130, or larger can deliver designs for considerably less. The lower costs result from several factors—masks are less expensive, chip complexities are typically lower, and thus the design-verification cost will drop.

Once a design is complete, it often becomes necessary to migrate to a higher-performance or more economical process. To this end, many ASIC vendors possess cell libraries that span different process nodes. Transitioning to the next process node may require considerable effort to re-verify the design, though (see "Process Migration For IP And ASICs," p. 61).

One major advantage that cell-based ASICS have over other-ASIC solutions is the ability to combine analog and digital functions on the chip, creating a true single-chip system. Today's mixed-signal ASIC processes can deliver RF front ends, analog-to-digital and digital-to-analog converters, voltage references, and many other functions not offered as standard features on the new platform and structured ASICs or on most field-programmable gate arrays (FPGAs).

With a broader mix of on-chip functions available for cellbased ASICs, designers can craft chips for applications that range from wireless communications, networking, and computing to industrial and consumer systems. To design such systems-on-a-chip (SoCs), general-purpose electronic-designautomation (EDA) tools can be assembled into a design-flow suite that starts with design capture and goes through final layout and verification.

Still, selecting the proper tools for a particular application segment can pose a significant challenge. One approach offered by Cadence Design Systems creates application-specific collections of tools that target specific market segments. Such design kits supply a proven design flow and a set of tools selected to meet the needs of that market segment (see "Streamlining The ASIC Design Process" online at www., Drill Deeper 11342).

PLATFORM/STRUCTURED NICHE The market niche formed by the latest platform and structured array offerings provide designers with a lower-cost alternative to full cell-based ASICs. But platform and structured solutions tend to be digital-only implementations. They carry limited mixed-signal functionality in the form of phase-locked loops (PLLs), high-speed serial interfaces, and serializer/deserializer (SERDES) channels.

Standard pre-defined chips from platform and structured ASIC vendors cut development costs by trimming mask costs, as well as the time and cost to verify a significant portion of the system logic. Trimming development costs is, of course, paramount among designers. It has established a significant market niche for the platform and structured solutions.

These solutions attack the problem by offering a fixed set of resources prefabricated in the silicon. Designers then need to only overlay their logic and define from one to five metal wiring layers to configure the logic.

Platform and structured ASICs are similar in basic concepts. They both have an internal array of logic cells with dedicated memory blocks distributed in the logic fabric, and a ring of I/O cells surrounds that fabric.

Platform ASICs tend to be more feature-rich, packing multiple PLLs, multigigabit SERDES I/O channels, and higher gate densities than structured ASICs. A simple automotive analogy might classify a structured ASIC as a basic sedan, while a platform ASIC might be categorized as a luxury vehicle.

The up-front design costs for a multimegagate chip ( defining the circuit, implementing the various logic blocks, synthesizing the logic, and placing and routing the design) don't differ much from process node to process node (130 to 110, or 110 to 90 nm). Yet significant cost differences will crop up in the back-end portion of the design (design verification, timing closure, and mask creation).

In full cell-based ASIC designs, all cells are implemented from the base silicon levels through final metallization. A complete chip analysis (timing, design-rule checks, design verification, etc.) then must be done prior to mask creation. With platform and structured devices, the silicon can be preverified. Many of the library building blocks also can be preverified, reducing the back-end effort and speeding the time to fabrication.

Many of the vendors that offer full cell-based ASIC capabilities now also bring either structured or platform options to the table. They include AMI Semiconductor, Fujitsu, LSI Logic, NEC, and Toshiba.

In addition, the market opportunity has spawned startups like ChipX ( formerly named Chip Express), eASIC, eSilicon, Faraday, and Lightspeed to offer budget-priced solutions. Although FPGAs have reprogrammable platforms that almost fit the definition of structured or platform ASICs, all but the Altera Hard Copy families still use RAM, flash, or antifuses to configure the logic. Therefore, the former don't quite fit the definition of a hardwired platform or structured ASIC.

LARGE AND SMALL CELLS The actual cell architecture employed inside the platform and structured arrays determines how many layers of metallization are needed, and thus the non-recurring engineering (NRE) costs for the mask set. Most of the platform solutions utilize fine-grain architectures that use a small simple element, such as a two-input NAND gate, as the basic building block for the logic fabric.

Such an approach requires more custom levels of metal wiring—typically three to five layers. In contrast, most of the structured solutions leverage a large-grain architecture that employs a more complex basic cell and requires fewer layers of interconnections (typically one to three). However, such an architecture is less flexible.

Probably the largest selection of finegrain platform ASICs comes from LSI Logic, which has over 30 different chip configurations (Fig. 1). Most of those now come on the company's 110-nm process, but a few are still offered on the less expensive and less dense 180-nm process.

The company groups the platform chips into two main categories—compute optimized and network optimized. The compute-optimized chips, the Integrator series, pack lots of gates and memory blocks. The network-optimized chips, the Xtreme series, include SERDES channels as well as a large amount of logic and memory.

Based on a 110-nm process, the Integrator series packs up to 3.7 Mbits of RAM, up to 4 million gates, multiple PLLs, and I/O ports capable of 200-MHz double-data-rate (DDR) memory support. The configurable I/O pins range from 171 to 803, depending on package and chip option.

The newer Integrator 2 family uses a similar process, but it is more memoryintensive—it provides up to 8.2 Mbits of RAM and as many as 5 million gates. The I/O memory support was upgraded to handle DDR2 speeds of up to 266 MHz and from 135 to 930 configurable I/O pins.

With its four high-performance Giga-Blaze SERDES channels that run at up to 4.25 GHz, the Integrator QS series trims memory and gate capacity to 1.3 Mbits and 2.9 million gates. Like the Integrator series, this family offers a 200-MHz DDR memory interface capability, but with 144 to 721 configurable I/O pins.

The Xtreme family raises the SERDES ante by offering as many as 32 channels plus increased memory and logic (2.5 Mbits and up to 5 Mgates). It trims the number of available configurable I/O pins, though (259 to 590). The latest Xtreme2 series provides even more integration, with up to 48 Giga-Blaze SERDES channels that can run at 4.25 Gbits/s and as many as 40 3.2-Gbit/s SERDES channels based on LSI's Hydra architecture. Most of the slices in this family support DDR2 data rates while packing four PLLs and from 358 to 650 configurable I/O pins.

Fujitsu serves up two chip families in its AccelArray series, the Megaframe and Gigaframe platform ASICs. Both lines take advantage of 110-nm technology and employ a complex multielement logic cell that sits between the fine-grain and coarse-grain categories (Fig. 2, top).

The Megaframe versions pack from 696 to 1176 I/O cells and up to 2.8 million usable gates (4.7 Mgates total). On-chip SRAM ranges from 1.7 to 4.5 Mbits. Each member in this family packs eight PLLs. The largest version includes an ARM926EJ-S 32-bit processor core.

The Gigaframe series adds multiple four-channel multigigabit G-PHY interfaces as well as S-PHY interfaces. Its configurable I/O ranges from 554 to 760 cells. Meanwhile, the chips offer up to 3.1 million usable gates and up to 4 Mbits of RAM.

SPEEDY SERDES I/Os HIT 10 GBITS/S The instant silicon solution platform (ISSP) family from NEC somewhat straddles the fence between the platform and structured ASIC categories. The latest ISSP90 series is based on a 90-nm process technology. Its chips pack up to 6.5 million usable gates and up to 5.7 Mbits of embedded configurable memory. They also can operate at up to 500 MHz. The ISSP90-HSI's embedded SERDES cores will run at up to 10 Gbits/s.

Unlike the LSI RapidChip platform ASICs, the NEC ISSP structured platforms employ a complex logic cell that includes combinatorial logic and sequential logic (a flip-flop) (Fig. 2, bottom). So, only two custom metal layers are needed to configure the chip, keeping a cap on fabrication costs.

Also keeping masking levels to a minimum, designers at eASIC crafted a family based on 130-nm process features. The flexASIC series combines configurable lookup-table cells (similar to those used in RAM-based FPGAs) and mask-customized interconnects (Fig. 3). As a result, the company can reduce the masking to a single metal layer, which can be patterned using a direct-write electron-beam lithographic system. That eliminates the mask for prototypes and even modest production quantities, dropping the NRE charges to near zero.

Chips in the family will offer between 250k and 3 million ASIC gates, plus up to 2.8 Mbits of dedicated block RAM. Even more memory is possible by using some distributed RAM in the lookup tables and sacrificing some logic. The maximum number of available user I/O pins ranges from 118 to 744, depending on the chip selected.

The combination of RAM-based lookup tables and e-beam-configured wiring places the chips between FPGAs and structured ASICs, leveraging the best of both. No programmable wirerouting matrices are required. Consequently, chip area is much smaller than an FPGA. But due to the complex logic cells, it's larger than what a structured ASIC could achieve. If your applications can fit in the density and performance window, though, this approach can be very economical and provide a quick time-to-market.

Dedicated PCI Express resources on its structured ASIC chips separate the ChipX CX6100 family from the rest of the structured ASIC field. This family of 130-nm structured chips features a silicon-proven PCI Express physical-layer (PHY) core. The core offers complete PIPE (PHY interface for PCI Express) interoperability for designers who plan to use their own PCI Express controller logic. When used with the optional PCI Express controller from ChipX's library, the PCI Express subsystem can be configured in the logic fabric and support one, four, or eight lanes.

Twelve prefabricated chips make up the CX6100 series, with gate counts ranging from 240k to 1.8 million. The chips will pack up to 1.1 Mbits of RAM and operate at system clock speeds of 250 MHz. Their fine-grain logic fabric can be customized with two, three, or four layers of metal, depending on the customer's priority in terms of density and time-to-market.

ON A BUDGET How can you lower the cost of designs based on very-highgate-count FPGAs? Replace the FPGAs with a structured ASIC optimized to drop into the FPGA socket. Altera offers that alternative with its Hard Copy and Hard Copy II families, which can replace the Stratix and Stratix II families of FPGAs.

Similarly, AMI Semiconductor's XpressArray II family is a low-cost replacement for the Altera APEX-II and Stratix FPGAs or the Xilinx Virtex II and Virtex II-Pro FPGAs. The XpressArray II chips pack up to 4.8 million ASIC gates and from 332 kbits to 4.8 Mbits of dedicated configurable memory (6.1 Mbits if the distributed lookuptable memories are included).


Altera Corp.

AMI Semiconductors Inc.

ChipX Inc.

eASIC Corp.

eSilicon Corp.

Faraday Technology Corp.

Fujitsu Microelectronics America Inc.

Lightspeed Semiconductor

LSI Logic Corp.

NEC Electronics America Corp.

PalmChip Corp.

Toshiba America Electronics Components Inc.


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