By using a combination of power-conserving tricks, a dual voltage-output DAC
draws less than 20 æA from a 5-V supply (). The circuit suits a need for programmable voltage generation
in slow or static applications, such as the nulling of offsets in a micropower
instrument.
Current-output DACs typically waste power by routing the complement of Iout
to ground. In this setup, that waste is avoided by operating each DAC in the
reverse voltage-switching mode. The reference voltage is applied to the pins
normally labeled Iout.
The Iout pins possess a constant and relatively low input impedance
of 11 kΩ. To reduce input currents, the reference voltage is scaled by
100 (from 5 V to 50 mV), and therefore delivers only 5 µA to each DAC
input. Signal levels are restored by a compensating gain of 100 in each output
amplifier. Inexpensive 10 M/100 k resistor networks are a good choice for the
multiple 100:1 attenuators required. Though only 2% accurate, they offer much
better capabilities in matching and tracking.
Greater scaling is impractical because of 0.5 mV (maximum) offsets in the
output amplifier shown in the figure. Amplified by 100, these offsets produce
worst-case output errors of ±1% (0.05 V). The errors are constant over
temperature, but additional error due to drift over a range of 40°C is typically
±1/2 LSB. These micropower op amps are chosen for low supply current—their
typical IDD is only 1 µA.
The last requirement for minimizing the overall current drain is to ensure
that logic signals applied to the digital inputs of IC1 swing to within 0.2
V of each rail. The maximum specified IDD for that condition is 100
µA over temperature, but this specification (like most CMOS IDD
ratings) is extremely conservative. IDD is negligible for rail-to-rail
swings, but rises dramatically as the swings approach TTL levels.
