The U.S. Coast Guard transmits differential corrections to
GPS signals (DGPS) via low-frequency (285- to 325-kHz)
beacons. Transmission data rates are 100 or 200 bits/s. The
modulation is minimum-shift keying (MSK), resulting in a pseudo
frequency-shift keying (FSK) with a carrier shift of half the bit
rate. For a 100-bits/s signal, the carrier shift is only ±25 Hz. With
a receiver IF frequency of 1 kHz, the IF signal shifts between 975
and 1025 Hz. The two data tones correspond to times of 1026 µs
and 976 µs, respectively.
Initial attempts to detect the modulation centered on phaselocked
loops and analog discriminators, all of which needed to be
optimized for each data rate or tweaked. There was also concern
about the effects of aging components. Consequently, we developed
a digital technique using 5-V CMOS circuitry that measures
the length of each cycle of the IF signal. The circuit works well
with ac-coupled IF signals from 2 V p-p to 15 V p-p.
A CD4049 CMOS hex buffer/converter clips the IF input signal
(see the figure). The CD4049 is followed by a CD4013 D-type
flip-flop configured as a toggle flip-flop to remove any hysteresis.
The positive and negative portions of the signal are processed
separately. The negative portion of the square wave gates a
1000-bit counter that is fed from a 1.000-MHz clock.
If the signal’s duration is longer than 1000 µs, there will be an
overflow pulse. If the
duration is shorter
than 1000 µs, there’s
no overflow. Similarly,
the duration of the
positive portion of the
IF-generated square
wave is measured by a second CD4059. Feeding the outputs of
the two CD4059s to an OR gate merges the measurements of
every cycle of the data IF signal.
Any overflow pulses trigger a CD4098 retriggerable monostable
multivibrator. The output pulse length is 1.1 ms. Having an
output pulse length slightly greater than the period of the IF center
frequency ensures that the output pulse will not drop to zero
between adjacent long-duration cycles of the IF signal.
The reset command of the CD4059s used as programmable
dividers isn’t straightforward. If control inputs Kb and Kc are set
to zero, the counter resets to the jam inputs.
Since a divide-by-ten was desired for the counter first stage,
Ka = 1, Kb = 1, and Kc = 0. Kc is always zero, so the Kb control
was used for reset. After a master reset, there’s one extra count.
Therefore, with a jam input of 1000, the output pulse occurs after
1001 counts. If this is a problem, the jam input could be set to 999
to get an overall delay of 1000 µs.
Because the CD4059 is a synchronous programmable counter,
the output pulse is one clock cycle—1.0 µs. Using a jam
input of 1000, there are no output pulses for pulses shorter than
999 µs, and there are continuous pulses for pulses longer than
1002 µs.
The lengths of the detected data pulses are very close to multiples
of 10 ms, with a maximum error of only 0.1 ms. Triggering
an oscilloscope on the rising edges of the data pulses, the IF signal
appears as a pure sine wave of 975 Hz. When the scope is triggered
on the falling edges, the raw IF signal appears as a pure sine
wave of 1025 Hz. Because the circuit functions as a frequency
discriminator centered on the IF frequency, the detection scheme
is independent of the transmission data rate.
