Interface Controller Cores Expand Communications Market Possibilities

The company, in conjunction with Xentec, has developed four new AllianceCORE products for use in its Virtex series FPGAs. The new cores include UTOPIA Level 3 master and slave transmitter and receiver interface controllers and target cell-based communications applications, including asynchronous transfer mode (ATM) systems. All of the cores are compatible with the ATM forum's UTOPIA Level 3 specification and are said to be flexible and configurable for 8-, 16-and 32-bit bus widths and cell formats from 52- to 56-octets. The ATM-side controller cores can support one PHY device in single-PHY mode or up to 32 PHY devices in multiple-PHY mode. The source code versions of the cores are completely configurable and can be purchased directly from Xentec.