Embedded PGA Cores Stretch SoC Design Flexibility

Designed in 0.18-µm CMOS SRAM technology, the VariCore family of embedded programmable gate array (EPGA) IP cores is claimed to be the first broadly available commercial, embeddable and reconfigurable soft hardware IP products for ASIC and ASSP systems-on-a-chip (SoCs). The cores are based on a three-input look-up-table structure and consist of primary embedded gate blocks of EPGAs, with each block consisting of 2,500 ASIC gates.
The scaleable, configurable PEG blocks are presently used to create from a 2x1 EPGA core of 5,000 ASIC gates to a 4x4 core of 40,000 gates. The VariCore EPGA cores can handle system clock speeds of up to 100 MHz. Other core features include: a large number of I/O ports; built-in controllability and observability; in-system programmability; VariCore compiler software; built-in self test (BIST) interface; 1.8V operating voltage for clock speeds up to 250 MHz; and core power dissipation of 0.075 µW/gate/MHz.