It’s Time To Start Using PCI Express Gen 3

March 4, 2011
PCI Express Gen 3 runs at 8 Gtransfers/s. Its 128b/130b encoding reduces overhead from about 20% to 1.5%.

PLX Technology 48-lane, 12-port PEX8748

PLX Technology Java-based GUI diagnostics

USB 3.0, SATA III, and 6-Gbit/s SAS are the next-generation peripheral and storage subsystem interfaces. Shipping now, they take advantage of PCI Express Gen 2 platforms. PCI Express Gen 2 runs at 5 Gtransfers/s, but PCI Express supports multiple links. For example, graphics adapters typically use x16 links. PCI Express can easily handle the peripheral and storage subsystems.

PCI Express Gen 3 is the next performance leap (see “PCI Express 3.0 Nears The Station” at It kicks the transfer rate to 8 Gtransfers/s, and its throughput almost doubles because of the switch from Gen 1’s and 2’s 8b/10b to Gen 3’s 128b/130b, reducing overhead from about 20% to 1.5%.

The standard includes a host of new features, including a dynamic power adjustment mechanism and atomic operations. The enhanced multicast support targets embedded and communication applications. It also provides address-based support.

Getting Started With Gen 3

PLX Technology has announced a range of PCI Express Gen 3 switches, from the 12-lane, three-port PEX8712 to the 48-lane, 12-port PEX8748 (Fig. 1). The PEX8712 comes in a 19- by 19-mm package while the PEX8748 comes in a 27- by 27-mm package. Pricing starts at $30.

These switches will need to be used with a processor that also supports PCI Express Gen 3, although they could be used as the backbone of a larger switching system linking PCI Express Gen 2 processors and devices. As with Gen 2, Gen 3 is backwards compatible.

PLX Technology has also released a software development kit (SDK) designed to support the company’s Gen 3 switches. Its serializer-deserializer (SERDES) measurement system takes advantage of on-chip diagnostic hardware (Fig. 2). The Java-based GUI is just part of the software in the SDK software.

The on-chip hardware and software are called visionPAK. The combination of access to on-chip registers and monitoring systems can potentially eliminate the need for more costly, external test equipment such as logic analyzers, traffic generators, and oscilloscopes.

The SDK’s interface is through the I2C configuration port found on PLX Technology’s Gen 2 and Gen 3 switches. The SDK also lets developers take advantage of other hardware found on the PLX Technology switches. For example, the chips have DMA controllers. They also have packet generators, so one switch can be used to test another. A built-in performance monitor can track the load.

The SDK includes kernel drivers for popular operating systems like Microsoft Windows and Linux. So, transfers can be offloaded to the switch.
PCI Express Gen 3 will show up later in 2011, which is plenty of time for most of us and just in time for power developers. It provides higher throughput while using the same or less power than Gen 2. It may also require more robust retimers like IDT’s eight-lane TO816P PCI Express Gen 3 retimer, which eliminates deterministic jitter and random jitter (see “Retimer Cleans Up PCI Express” at

PLX Technology

About the Author

William G. Wong | Senior Content Director - Electronic Design and Microwaves & RF

I am Editor of Electronic Design focusing on embedded, software, and systems. As Senior Content Director, I also manage Microwaves & RF and I work with a great team of editors to provide engineers, programmers, developers and technical managers with interesting and useful articles and videos on a regular basis. Check out our free newsletters to see the latest content.

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I earned a Bachelor of Electrical Engineering at the Georgia Institute of Technology and a Masters in Computer Science from Rutgers University. I still do a bit of programming using everything from C and C++ to Rust and Ada/SPARK. I do a bit of PHP programming for Drupal websites. I have posted a few Drupal modules.  

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