Intel's 3D tri-gate transistor architecture
3D gate electrode that controls silicon fin
Intel demonstrated its new 3D tri-gate transistor architecture (Fig. 1) that is used in the 22nm Ivy Bridge processors. The processors and transistor architecture is designed for high volume manufacturing (HVM). The 3D design uses a gate electrode that controls silicon fin from three sides (Fig. 2). This improves the sub-threshold slope. The increased inversion layer area and the use of multiple drive fins allows higher drive currents.
Reducing leakage current at 22nm is critical. The fully depleted tri-gate transistor does this because it has a steep sub-threshold slope compared to the more conventional planar transistor. Alternatively, the steeper sub-threshold slope can be used lower the threshold voltage. This means the transistor can operate at a lower voltage while operating at faster switching speeds than planar transistors.
Intel's approach can provide a 37% performance improvement at a lower voltage than a planar architecture. It can cut power requirements in half while maintaining constant performance. The 3D architecture improves switching characteristics and it provides a higher drive current for a given area.
The implementation adds about 2% to 3% to the cost. The alternative fully deplete silicon on insulator (FDSOI) architecture would add 10% to the chip cost. Overall, the 3D tri-gate approach is a significant improvement versus partially depleted silicon on insulator (PDSOI), FDSOI and bulk designs.
Intel continues to push transistor technology so it follows Moore's Law. It looks like silicon still has plenty of performance left, with the right transistor design.