ACE Cache Line States and their alternative MOESI naming
Arm microcontroller cores take advantage of Arm's AMBA 4 interface. The latest version incorporates the AMBA 4 AXI Coherency Extensions (ACE). AMBA 4 was launched last year. The new spec targets heterogeneous multicore processor clusters including processors such as the ARM Cortex-A15 MPCore and the ARM Mali-T604 graphics processor. It provides a standard mechanism for managing cache coherency, memory barriers and virtual memory.
The system supports the 5-state MOESI cache coherency model. The ACE cache line states (Fig. 1) map directly to this model. ACE is designed to perform direct master-to-master data transfer when possible. This improves performance because off-chip access is often ten times that of on-chip communication.
The latest standard employs memory barriers throughout the memory sub-system. This allows system architects to ensure optimal instruction ordering in most instances.
ACE allows designers to handle distributed virtual memory support utilized by cores like the Cortex-A15. The ARM Cortex-A15 MPCore is the first core to support AMBA 4 AXI ACE. Multicluster systems share a single set of MMU (memory management unit) page tables. A page table update by one master invalidates translation look-aside buffers (TLB) using a broadcast ACE invalidation message.
The CoreLink CCI-400 Cache Coherent Interconnect from Arm incorporates a pair of ACE coherency ports. This enables two CPU clusters allowing hthe design of systems with up to 8 Cortex-A15 CPU cores. The CCI-400 also handles up to three master interfaces for memory controller and peripherals ports.
