According to Altera, version 13.0 of its Quartus II FPGA design software promises a 25% reduction in compile times for 28-nm FPGAs and SoCs, on average, with up to 50% reduction for the most difficult 28- nm Stratix V FPGAs. The company also says that this Quartus II version makes it possible to achieve the fastest maximum operating frequency (Fmax) for FPGAs. The release includes enhancements to the development suite’s high-level C-based, system-/IP-based, and model-based design flows. A software development kit for OpenCL opens the doors to massively parallel FPGA-based accelerators to software programmers without FPGA experience. A new Qsys system integration tool provides expanded support for ARM-based Cyclone V SoCs. In addition, a new DSP Builder design tool helps with the implementation of high-performance fixed- and floating-point algorithms into DSP designs.